哈工大数字逻辑unit13资料课件.ppt

1、Programmable Logic Devices张彦航张彦航School of Computer ScienceZUnit 13 Programmable Logic DevicesnRead-Only Memories nProgrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable Logic DevicesnField-Programmable Gate ArraysPLDlow density PLD（LDPLD）High density PLD（HDPLD） EPLD CPLD FPGAROMPLA

2、PALGALProgrammable Logic Devices ROMPROMEPROMRead-Only MemoriesErasable, floating-gate technologyProgrammable , add a fuse to the deviceProgrammable Logic Devices Electrically erasable programmable ROMsDevelopment History of PLDPROMPLAGALFPGAEPLDCPLDSoPCProgrammable Logic Devices Unit 13 Programmabl

3、e Logic DevicesnRead-Only Memories nProgrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable Logic DevicesnField-Programmable Gate Arrays字字（Word） 地址地址（Address ）n Each of the output patterns that is stored in the ROM is called a wordn Each memory cell n Each combination of n inputn wh

4、ich can select one of the 2n words stored in the memoryROM Address: N-bit 2N words can be stored1. ROMn input lines and m output lines ncontains an array of 2n words, each word is m bits long. nThe input lines serve as an address to select one of the 2n words. nWhen an input combination is applied t

5、o the ROM, the pattern of 0s and 1s which is stored in the corresponding word in the memory appears at the output lines。ROMn input lines and m output linesn contains an array of 2n words, each word is m bits longn Typical size： 2n mROM 输入缓冲器输入缓冲器（input buffer）不同于三态门不同于三态门ROM interconnection points固定

6、连接固定连接可编程连接可编程连接不连接不连接+DecoderMemory array+ABF3 F2 F1 F000m0 =1(m1 =0, m2=0, m3 =0)0 0 1 001m1 =1(m0 =0, m2=0, m3 =0)0 1 0 110m2 =1(m0 =0, m1=0, m3 =0)1 1 0 111m3 =1(m0 =0, m1=0, m2 =0)1 1 1 0F0 = m1+ m2 = AB+ABF1 = m0+ m3= AB+ABF2 = m1+ m2 + m3= AB+AB+ABF3 = m1+ m2 + m3= AB+ABROMdirectly implements

7、 a truth tableROM X ( or ) ： indicates that the switching element is present and connected no X ( or ) indicates that the corresponding element is absent or not connected.ROM ABF0F1F2F3m0m1m2m3ROM +Applications1. Design Combinational Circuit F1 （3，4，6，7），）， F2 （0，2，3，4，7） Design a functional operati

8、on table: x=B3B2B1B0 : 015yx2: 0152y Y7Y6Y5Y4Y3Y2Y1Y0Applications2. Design functional operation table ROM 输 入输 出注B3 B2 B1 B0Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0十进制数0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 0 0 0 0 0 0 00 0 0 0 0 0 0 10 0 0 0

9、 0 1 0 00 0 0 0 1 0 0 10 0 0 1 0 0 0 00 0 0 1 1 0 0 10 0 1 0 0 1 0 10 0 1 1 0 0 0 10 1 0 0 0 0 0 00 1 0 1 0 0 0 10 1 1 0 0 1 0 00 1 1 1 1 0 0 11 0 0 1 0 0 0 01 0 1 0 1 0 0 11 1 0 0 0 1 0 01 1 1 0 0 0 0 10149162536496481100121144169196225m0m1m2m3m4m5m6m7m8m9m10m11m12m13m14m15与门阵列(地址译码器)或门阵列(存储矩阵)Y7 Y

10、6 Y5 Y4 Y3 Y2 Y1 Y0B3 B3 B2 B2 B1 B1 B0 B0RealizeApplications3. Design a sequential circuit to convert BCD to excess-3 codeROM State graph and state table Reduction of State Table State AssignmentROM ROM Transition tableROM 2. PROM（programmable ROM） No fuse is broken for a new PROM chip, each memory

11、 cell stores “1”. Rewrite only oncePROM Code ConverterAddress of PROMstored inPROM PROMDirectly implements a truth tableConvert 4-bit binary code to Gray codePROM Example PROM Example9 9151313101012121111T883123456871616VccCEA4 A3 A2 A1 A0 F7F0 F1 F2 F3 F4 F5 F6 Gnd1414VccT883328 bit PROMPROM +G2G1G

12、3G4B4B8B2B1G4 = B8G3 =+B8B4G2 =+B2B4G1 =+B2B1Solution 2PROM Applications3. Design a beat generator with PROMF4F3F2F10 1 2 3 4 5 6 7 00 1 4 5 0 1 2 5 6 4 5 6 7 PROM ExampleA2A1A0m0 m1 m2 m3 m4 m5 m6 m7F4F3F2F1模模8计计数数器器F4F3F2F10 1 2 3 4 5 6 7 00 1 4 5 0 1 2 5 6 4 5 6 7 n将字符点阵存放在将字符点阵存放在PROMPROM中中n逐行读取

13、字符点阵，并送往显示器件逐行读取字符点阵，并送往显示器件specification standards97，77，75 ， 85 Applications 4. 字符发生器字符发生器（ Character Generator） PROM Examplem0 m1m2 m3 m4 m5 m6F0F3F2F1Q2Q1Q0F4F0F3F2F1F4Q2 Q1 Q0F4 F3 F2 F1 F00 0 00 0 10 1 00 1 11 0 0 1 0 11 1 01 1 1 1 11 0 0 0 01 0 0 0 01 1 1 1 01 0 0 0 01 0 0 0 01 1 1 1 175Design

14、 a library of 64 characters, each character is stored by a 85 dot matrix decoderaddressCharacter address A2A0: select a row of one character A8A3: select one of 64 charactersPROM Example1616Typical Chips PROM： Texas TBP28S42 TBP34R162 EPROM: Intel 2716（2K8 bit） 27C202C （16K16 bit） 27C040 （512K8 bit

15、) Unit 13 Programmable Logic DevicesnRead-Only Memories nProgrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable Logic DevicesnField-Programmable Gate ArraysROMm0 . m7 F0F3F2F1A2 A1 A0F0 F1 F2 F30 0 00 0 10 1 00 1 11 0 0 1 0 11 1 01 1 10 0 0 0 0 1 1 1 0 1 1 10 0 1 0 0 1 1 10 0 1 1 0

16、 0 1 0 1 1 1 0 A2A1A0Problem：wasting of resourcesProgrammable Logic Arrays PLA nBoth of the AND array and the OR array are programmablenimplements a minimum sum-of-products expression nmust simplify logic equationsncontain flip-flops with inputs driven from programmable array logic.Programmable Logi

17、c Arrays PLA Programmable Logic Arrays Design with PLA PLA implements a minimum sum-of-products expression zero, one, or more rows may be selected by each combination of input values.If abcd =0001, no rows are selectedIf abcd =1001, only the third row is selected, f1f2f3=101. If abcd= 0111, the firs

18、t, fifth, and sixth rows are selected.PLA Design F（0,2,3,4,5,11,13,14,15）using PLA 0 01 1001 11 11 10 00 00 0111 11 101 00 01 11 1000011110A BCDF=ACD+BCD+ABC+ABC+ACDPLA: 5 wordsROM：9 wordsFABCDExampleDesign F1=(3,4,6,7)， F2=(0,2,3,4,7）using PLAExampleConvert 4-bit binary code to Gray codeExample Com

19、pare using PROM1 1 1 0 0 0 0 1 01 0 0Design a up-down 2-bit binary counter with JK flip flops and PLA.X=0: up; X=1:down; Y: carry ( or borrow)X/YQ2Q10011100/01/01/11/01/00/00/10/0010 0 0 0 0 1 0 1 00 1 1Y Q Q Q Q X1n1n nn 12121 0 0 1 0 11 1 01 1 10 1 0 1 0 0 1 1 00 0 1 state graph transition tableEx

20、ample RealizeJC1KJC2KX1CPQ1Q2YnnQXQXKJKJ1122111 Design mode-12 counter with Seven-Segment and PLAy4 y3 y2 y1 y4n+1 y3n+1 y2n+1 y1n+1 J4 K4 J3 K3 J2 K2 J1 K1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 1

21、 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1PLA Example0 01 1000 00 000 00 01 11 1000011110y4y30 01 100 00 01 11 1000011110J4K40 00 0000 01 100 00 01 11 1000011110J30 01 100 00

22、 01 11 1000011110K3y4y3y4y3y2y1y2y1y4y3101010 00 01 11 1000011110J2y4y3y2y10 01 10 01 10 01 1 00 01 11 1000011110K2y4y3y2y1y4y3 y2y1 a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 1 1 0 1

23、 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 01 0 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1y4y3 y2y1 a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 2 0 0 1 1 1 1 1 1 0 0 1 3 0 1 0 0 0 1 1 0 0 1 1 4 0 1 0 1 1 0 1 1 0 1 1 5

24、 0 1 1 0 0 0 1 1 1 1 1 6 0 1 1 1 1 1 1 0 0 0 0 7 1 0 0 0 1 1 1 1 1 1 1 81 0 0 1 1 1 1 0 0 1 1 9 1 0 1 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1aby4y3y2y10 1 2 11gabgCPy2y1J1 10 J2 10J3 10 J4 10y3y4十十位位个个位位K1K2K3K4“1”Rdy1y2y3y4Design a Sequential Lock with PLA Inputs: X1X2，Output: Z States: R、B、C、E I

25、nput 00 01 11 Sequentially from X1X2 state of the lock will be changed from R to B and then to C，and Z1（unlock） If the order is not above mentioned, state of the lock will be E（error） state of the lock will be reset to R whenever 00 are inputted from X1X2ExampleDerivation of State Graphs and Tables

26、0 0 0 1 1 1 1 0 Z R R B E E 0 B R E C E 0 C R E E E 1 E R E E E 0SRreceive 00 Breceive 01 after 00, Creceive 11 after 00 , 01, Z 1（unlock） Eerror2. Reduction of State Table3. State AssignmentR 00 、 B 01C 11 、 E 10 N=4, 22 4 k = 2 flip flops4. transition tableDesign a Sequential Lock with PLAX1 X2 Y1

27、 Y2 Y1n+1 Y2n+1 J1 K1 J2 K2 Z Z0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 10 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 00 1 1 0 1 0 0 1 1 1 1 001 1 0 0 1 0 1 0 01 1 0 1 1 1 1 0 01 1 1 0 1 0 0 0 01 1 1 1 1 1 0 0 1J1 = X1 K1 = X1 X2 1 11 1111 11 11 11 11 11 1000 00 000 00 01 11 1000011110X1 X2Y1 Y2

28、Y1n+1Y1n+1 = X2Y1+X1 =(Y1 +Y1) (X2Y1+X1 ) =X1Y1+X1Y1 +X2Y1 =X1Y1+(X1+X2 ) Y1Y2n+1 = X1 X2 Y1+X1X2Y2 =(Y2 +Y2) (X1 X2 Y1+X1X2Y2 ) =X1X2Y1Y2+X1X2Y1Y2 +X1X2Y2 =X1X2Y1Y2+(X1X2Y1 +X1X2)Y2 K2 = X2 +X1Y1J2 = X1 X2 Y1 00 00 00 00 01 11 10 000 01 11 100 00 00 0 00 01 11 1000011110X1 X2Y1 Y2Y2n+1Z = Y1 Y20 01

29、 1000 01 10 00 00 01 1000 01 100 00 01 11 1000011110X1 X2Y1 Y2J1 = X1 K1 = X1 X2 K2 = X2 +X1Y1ORJ2 = X1 X2 Y1 x1x2y1y2CPy1J1 10J2 10 y2K1K2ZRdZ = Y1 Y2J1 = X1 K1 = X1 X2 J2 = X1X2Y1 K2 = X2 +X1Y1x1x2y1y2CompareDesign a 1-bit FA with PLAExampleUnit 13 Programmable Logic DevicesnRead-Only Memories nPr

30、ogrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable Logic DevicesnField-Programmable Gate ArraysPALAND array： programmable OR array： fixedmust simplify the logic equations.Programmable Arrays LogicA2A1A0D0D1D2OR array FixedAND arrayprogrammablePALProgrammable Arrays Logic ),(),(),

31、(),(654321643221mCBAYmCBAYACCBBAYCABAY 21And array Or arrayABCY1 1Y2 2Programmable Arrays LogicExample用用PAL设计一个单行街道的十字路口交通信号控制器设计一个单行街道的十字路口交通信号控制器One-way: signed by 1 and 2X1 , X2: Sensor, Xi= 1 means road i has a car； Xi= 0 means road i has no carOutput: Red light (R), Green light (G), yellow ligh

32、t (Y)Programmable Arrays LogicExampleINIT: reset the system to the initial stateTraffic signal controllerProgrammable Arrays LogicS0initial state: Road 1: Rush through， Road 2: no enter S3 , S7 transition state of traffic conversionG1S0G1R2S1G1R2S2R2S3Y1R2S4R1G2S5R1G2S7R1Y2S6R1G2X1 X2X1 X2X1 X2X1 X2

33、X1 X2X1 X2X1 X2X1 X2State tableI1 = 1 I2 = 1 I3 = 1I4 = 1I0 = INIT = 1S0S1S2S3S4S5S6S7S0S0S0S0S0S0S0S0S0S1S2S3S4S5S6S7S0S2S3S4S4S6S7S2S0S0S0S2S3S4S6S6S7S2S3S4S5S6S7S1G1R2G1R2G1R2Y1R2R1G2R1G2R1G2R1Y2outputPresent stateNext stateLetX1122123124120IXINIT; IXXINIT;IXXINIT; IXXINIT;IINITI1=1 I2=1 I3=1 I4=

34、1 I0=1001 010 000 001 000010 010 010 010 000011 011 011 011 000100 100 100 100 000101 100 110 101 000110 110 110 110 000111 111 111 111 000000 000 000 000 0000 0 1 1 0 00 0 1 1 0 00 0 1 1 0 00 1 0 1 0 01 0 0 0 0 11 0 0 0 0 11 0 0 0 0 11 0 0 0 1 0R1 Y1 G1 R2 Y2 G2Q2 Q1 Q00 0 00 0 10 1 00 1 11 0 01 0

35、11 1 01 1 1present Q2(n+1)Q1(n+1)Q0(n+1)output 8 states，needs 3 flip flops, State Assignment: S0 S1 S2 S3 S4 S5 S6 S7 Q2Q1Q0： 000 001 010 011 100 101 110 111Programmable Arrays LogicRealize012012012201222201201201210121210120012001240124012101211)(n000120012001200120012301221)(n1101200120012001201)(

36、n22QQQQQQQQQGQQQYQRQQQQQQQQQGQQQYQRQQQIQQQI QQQIQQQIQQQIQQQIQDQQQIQQQI QQQIQQQIQQQIQQQIQDQQQIQQQIQQQIQQQIQD Select PAL16RP8 ChipProgrammable Arrays Logic 与与阵阵列列 B A L1 L0 可可编编程程 或或阵阵列列 固固定定 (PLA)(PROM)(PAL) 与阵列与阵列 B A L1 L0 可编程可编程 或阵列或阵列 可编程可编程 与与阵阵列列 B A L1 L0 或或阵阵列列 可可编编程程 固固定定 PROM, PLA and PALA0

37、A1A2 +OLMCOLMCOLMC与阵列与阵列或阵列或阵列输出逻辑宏输出逻辑宏GAL（General Arrays Logic）可编程与阵列（32X64位）8个反馈/输入缓冲器8个三态输出缓冲器12198个输出逻辑宏单元OLMC8个输入缓冲器29输出使能缓冲器GAL16V8 逻辑图时钟输入GALAUVWXYZJIGNDHQPNMEDCB12345678910191817161514131211Vcc20PLD16V8 BASIC GATES LI AND WANG 2003.06GATESB C D E M N P Q H GNDI J Z Y X W V U A VCC; EQUATION

38、SU =/AV = B*CW =D+EY =/P*/Q + P*QZ = /H+/I +/JDESCRIPTIONX =/M*/NGAL1356710191817161514131211202PR4TQQCLRDQQCLRJQQCLRPRPRK89PLD16V8BASIC FLIP-FLOPLI AND WANG 2003.06.06FFCLK S R PR T D J K CLR GNDOE QJC QJT QDC QDT QTC QTT QSC QST VCC;EQUATIONSQST:=/S+R*QSTQSC:=/R+S*QSC ;RS-TYPE FFQTT :=PR+/CLR*/T*Q

39、TT+/CLR*T*QTCQTC :=CLR+/PR*/T*QTC+/PR*T*QTT ;T-TYPE FFQDT :=PR+/CLR*DQDC:=CLR+/PR*/D ;D-TYPE FFQJT :=PR+/CLR*J*QJC+/CLR*/K*QJTQJC :=CLR+/PR*/J*QJC+/PR*K*QJT ;JK-TYPE FFDESCRIPTIONABEL样本文件样本文件2/4线译码器线译码器MODULE decoderDECLARATIONS a , b pin; y0 , y1 , y2 , y3 pin is type com ;TRUTH_TABLE ( a, b - - y0

40、,y1,y2,y3 ) 0, 0 - - 1 , 0 , 0 , 0; 0, 1 - - 0 , 1 , 0 , 0; 1, 0 - - 0 , 0 , 1 , 0; 1, 1 - - 0 , 0 , 0 , 1;END decoder属性说明属性说明 输输 入入 输输 出出a by0 y1 y2 y30 01 0 0 00 10 1 0 01 00 0 1 01 10 0 0 1同步模同步模4二进制递增计数器二进制递增计数器MODULE cnt4DECLARATIONS cp pin; q1 , q0 pin is type reg ; Co pin is type com ; s0=b00

41、; s2=b10; s1=b01; s3=b11;EQUATIONS q1,q0.clk = cp ;STATE_DIAGRAM q1,q0 STATE s0: GOTO s1 WITH Co = 0 ； STATE s1: GOTO s2 WITH Co = 0； STATE s2: GOTO s3 WITH Co = 0； STATE s3: GOTO s0 WITH Co = 1；END句尾句尾分号分号状态图段状态图段逻辑逻辑方程段方程段变量变量说明段说明段q1、q0的时钟由的时钟由cp提供提供属性说明属性说明ABEL样本文件样本文件类型类型 阵阵 列列 输输 出出 方方 式式 与与 或

42、或 PROM PLA PAL GAL 固定固定 可编程可编程 可编程可编程 可编程可编程 可编程可编程 可编程可编程 固定固定 固定固定 固定固定固定固定固定固定可编程可编程四种四种PLD的结构特点的结构特点 与门与门阵列阵列或门或门阵列阵列乘积项乘积项和项和项PLD主体主体输入输入电路电路输入信号输入信号互补互补输入输入输出输出电路电路输出函数输出函数反馈输入信号反馈输入信号 可由或阵列直接输出，构成组合输出；可由或阵列直接输出，构成组合输出； 通过寄存器输出，构成时序方式输出通过寄存器输出，构成时序方式输出。PLD的基本结构的基本结构Unit 13 Programmable Logic D

43、evicesnRead-Only Memories nProgrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable Logic DevicesnField-Programmable Gate ArraysComplex PLD :CPLDComplex Programmable Logic Devices1. Architecture of Xilinx XCR3064XL CPLDComplex Programmable Logic DevicesComplex Programmable Logic Devi

44、ces2. Xilinx CoolRunner-II Architecture（Advanced Interconnect Matrix） CoolRunner-II MacrocellApplicationsSoccer Robot Controller CPLD + DSPComplex Programmable Logic DevicesUnit 13 Programmable Logic DevicesnRead-Only Memories nProgrammable Logic ArraysnProgrammable Arrays LogicnComplex Programmable

45、 Logic DevicesnField-Programmable Gate ArraysFPGA FPGA ProgrammableConfigurable Logic BlocksProgrammable IOBProgrammable InterconnectionFPGA FPGAFPGAXilinx Virtex/ Spartan II CLBFPGASimplified CLBImplementation of LUTFPGAFPGAXC3S500EXC3S500EPQ208FPGAn Artix-7 FPGA芯片芯片n 高速高速USBUSB接口、以太网接口接口、以太网接口n 内置

46、加速度计、温度传感器、数字麦克风、扬声器等内置加速度计、温度传感器、数字麦克风、扬声器等n 5V5V供电，也可直接使用供电，也可直接使用USBUSB供电供电n 16 16个个LEDLED，1616个开关个开关n 8 8个数码管，个数码管，6 6个按键个按键n 两个三色两个三色LEDLED，5 5个扩展接口个扩展接口Xinlinx Nexys4 掌上移动实验室掌上移动实验室Applications 1radar signal processing 高速 D/A 高速 A/D 中频模拟信号 信号处理IP 信号处理IP 信号处理IP 信号处理IP 标准通信总线和协议 单芯片动态可重构信号处理器 超大

47、规模单芯片超大规模单芯片 FPGA 表示可编程逻辑表示可编程逻辑 信号处理IP 微处理器IP 微处理器IP 信号处理IP 信号处理IP 通信控制器 IP 微处理器外设 IP 信号处理IP 标准处理器外设接口 FPGAMicroBlaze Or PPC405 UART Or EthernetJTAG Default PROM XC18V Upgrade PROM XC18V 配置配置异常异常处理处理 CoolRunner CPLD 面向各种面向各种应用的应用的IP Cores Restructurable Logic Based on InternetWhy IRL ?Remote system

48、 upgrade bug fix reconstruction monitoringFPGAApplications 2IRL Design Based on SOPCSpartan II-E 30 万门万门FPGA PQ208 256K32 SRAM 8M32 SDRAM 2M32 FLASH RS-232 Port JTAG Download & Debug Port Power Manger 5V/3.3V/1.8V50MHZ Clock Button LED 32bit/33MHZ PCI Interface FEM Interface FPGA Expansion Module XC

49、9536XLPROMAM29LV004FPGAApplications 3General Board Design Based on SOPCFPGAUSB控制模块控制模块数码相机数码相机GSM/GPRS外扩外扩SRAM板载板载SRAMAvalon Tri-state BridgeFLASH用户逻辑用户逻辑SDRAMAvalon BUS + NiosII CPU + 用户指令用户指令 CMOS 数字摄像头数字摄像头数字摄像头数字摄像头控制模块控制模块 (SCCB总线总线)Applications 4Traffic accident processes FPGAApplications 4Tra

50、ffic accident processes Other applications Other applications 原理框图的设计原理框图的设计( (Functional block diagram ) ) 设计输入设计输入（Design Entry） 逻辑综合逻辑综合（ Synthesize ） 仿真仿真（ Simulation） 管脚定义管脚定义（Place & Route） 芯片下载调试芯片下载调试（Configuration） Development flow of FPGAFPGA原理框图的设计原理框图的设计(Functional block diagram )nDraw a