vhdl语言要素答辩课件.ppt

1、CHAPTER 2 vhdl language elementnCONSTANT Fbus:BIT_VECTOR:=“1011”；Defining one constant is primarily in order to make some volume easy to read AND modifyconstantconstantconstantconstantconstantnSIGNAL data：STD_LOGIC_VECTOR(7 DOWNTO 0);LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGN

2、ED.ALL;ENTITY example IS PORT(clk:INSTD_LOGIC;q:OUTSTD_LOGIC);END example;ARCHITECTURE a OF example ISSIGNAL temp:STD_LOGIC_VECTOR(0 TO 2);BEGINcount:PROCESS(clk)VARIABLE counter:STD_LOGIC_VECTOR(0 TO 2):=000;BEGINIF(clkEVENT AND clk=1)THEN counter:=counter+1;END IF;temp=counter;END PROCESS;output:P

3、ROCESS(temp)BEGINIF(temp=111)THEN q=1;ELSE q=0;END IF;END PROCESS;END a;nBIT:2-levellogic(0,1).SIGNAL x:BIT;-x is declared as a one-digit signal of type BIT.SIGNAL s1：BIT_VECTOR（15 DOWNTO 0）；）；BIT:2-level logic(0,1).SIGNAL w:BIT_VECTOR(0TO7);TRUE、FALSE Character literals:Single ASCII character of su

4、ch characters.Not synthesizable.CHARACTER（1）nstring literals:ASCII characters of such characters.Not synthesizable.nVATIABLE string_1:STRING(0 TO 3);nnstring_1:=“a b c d”;Physical literalsn20 s，100 ns，3 sec。Used to inform physical quantities,like time,voltage,etc.Useful In simulations.Not synthesiza

5、ble.note，warning，error，failureNATURALNon-negative integers(from 0 to+2,147,483,647).STD_LOGIC STD_LOGIC_VECTOR:9-valued logic system introduced in The IEEE 1164 standard.U initial valueX Forcing Unknown(synthesizable unknown)0 Forcing Low(synthesizable logic 1)1 Forcing High(synthesizable logic 0)Z

6、High impedance(synthesizable tri-state buffer)W Weak unknownL Weak lowH Weak high Dont careUser-Defined Data Types VHDL also allows the user to define his/her own data types.nTYPE integer IS RANGE-2147483647 TO+2147483647;n-This is indeed the pre-defined type INTEGER.nTYPE natural IS RANGE 0 TO+2147

7、483647;n-This is indeed the pre-defined type NATURAL.nTYPE my_integer IS RANGE-32 TO 32;n-A user-defined subset of integers.nTYPE bit IS(0,1);n-This is indeed the pre-defined type BITnTYPE my_logic IS(0,1,Z);n-A user-defined subset of std_logic.Subtypes The main reason for using a subtype rather tha

8、n specifying a new type is that,though operations between data of different types are not allowed,they are allowed between a subtype and its corresponding base type.nSUBTYPE my_logic IS STD_LOGIC RANGE 0 TO Z;n-Recall that STD_LOGIC=(X,0,1,Z,W,L,H,-).n-Therefore,my_logic=(0,1,Z).nSUBTYPE small_integ

9、er IS INTEGER RANGE-32 TO 32;n-A subtype of INTEGER.Example:Legal and illegal operations between types and subtypes.SUBTYPE my_logic IS STD_LOGIC RANGE 0 TO 1;SIGNAL a:BIT;SIGNAL b:STD_LOGIC;SIGNAL c:my_logic;.b=a;-illegal(type mismatch:BIT versus STD_LOGIC)b=c;-legal(same base type:STD_LOGIC)Data C

10、onversion VHDL does not allow direct operations(arithmetic,logical,etc.)between data of different types.Therefore,it is often necessary to convert data from one type to another.This can be done in basically two ways:or we write a piece of VHDL code for that,or we invoke a FUNCTION from a pre-defined

11、 PACKAGE which is capable of doing it for us.functionSTD_LOGIC_1164TO_STD_LOGIC_VECTOR(A)TO_BIT_VECTOR(A)TO_STD_LOGIC(A)TO_BIT(A)Convert BIT_VECTOR to STD_LOGIC_VECTORConvert STD_LOGIC_VECTOR to BIT_VECTORConvert BIT to STD_LOGICConvert STD_LOGIC to BITSTD_LOGIC_ARITHCONV_STD_LOGIC_VECTOR(A,bit leng

12、th)CONV_INTEGER(A)Convert INTEGER、UNSIGNED、SIGNED to STD_LOGIC_VECTORConvert UNSIGNED、SIGNED to INTEGERSTD_LOGIC_UNSIGNCONV_INTEGER(A)C o n v e r t S T D _ L O G I C t o INTEGERExample:Data conversion.LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;.SIGNAL a:IN UNSIGNED(7 DOWNT

13、O 0);SIGNAL b:IN UNSIGNED(7 DOWNTO 0);SIGNAL y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);.y=CONV_STD_LOGIC_VECTOR(a+b),8);-Legal operation:a+b is converted from UNSIGNED-8-bit STD_LOGIC_VECTOR value,then assigned to to y.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY sel1in4

14、ISPORT(a:IN STD_LOGIC_VECTOR(1 downto 0);d:IN STD_LOGIC_VECTOR(3 downto 0);f:OUTSTD_LOGIC);END sel1in4;ARCHITECTURE sel OF sel1in4 ISBEGINf=d(conv_integer(a);END sel;Synthesizable data types.Data types Synthesizable values BIT,BIT_VECTOR 0,1 STD_LOGIC,STD_LOGIC_VECTOR X,0,1,Z STD_ULOGIC,STD_ULOGIC_V

15、ECTOR X,0,1,Z BOOLEAN True,False NATURAL From 0 to 2,147,483,647 INTEGER From-2,147,483,647 to+2,147,483,647 SIGNED From-2,147,483,647 to+2,147,483,647 UNSIGNED From 0 to 2,147,483,647 User-defined integer type SUBTYPE Subset of any type(pre-or user-defined)OperatorsAssignment OperatorsnAre used to

16、assign values to signals,variables,and constants.They are:n Used to assign values to individual vector elements or with OTHERS.Example:Consider the following signal and variable declarations:SIGNAL x:STD_LOGIC;VARIABLE y:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL w:STD_LOGIC_VECTOR(0 TO 7);Then the followi

17、ng assignments are legal:x=1;-1 is assigned to SIGNAL x using=y:=0000;-0000 is assigned to VARIABLE y using:=w=10000000;-LSB is 1,the others are 0w 1,OTHERS=0);-LSB is 1,the others are 0OperatorsLogical OperatorsnUsed to perform logical operations.The data must be of type BIT,STD_LOGIC,or STD_ULOGIC

18、(BIT_VECTOR,STD_LOGIC_VECTOR,or STD_ULOGIC_VECTOR)The logical operators are:nNotes:The NOT operator has precedence over the others.The XNOR operator wasnintroduced in VHDL93.Examples:y=NOT a AND b;-(a.b)y=NOT(a AND b);-(a.b)y=a NAND b;-(a.b)(3)Arithmetic OperatorsUsed to perform arithmetic operation

19、s.The data can be of type INTEGER,SIGNED,UNSIGNED,or REAL.Also,if the std_logic_signed or the std_logic_unsigned package of the ieeelibrary is used,then STD_LOGIC_VECTOR can also be employed directly in addition and subtraction operations（4）Comparison OperatorsnUsed for making comparisons.The data c

20、an be of any of the types listed above.The relational(comparison)operators are:n=Equal ton/=Not equal ton Greater thann=Greater than or equal to（5）Shift Operatorsnsll Shift left logic positions on the right are filled with 0snsrl Shift right logic positions on the left are filled with 0sSIGNAL g，h，i

21、：STD_LOGIC；SIGNAL c，d，e：STD_LOGIC _VECTOR（1 TO 0）；）；d=i&NOT h；a=c&d；nThe pre-defined,synthesizable data attributes are the following:n dLOW:Returns lower array indexn dHIGH:Returns upper array indexn dLEFT:Returns leftmost array indexn dRIGHT:Returns rightmost array indexn dLENGTH:Returns vector siz

22、en dRANGE:Returns vector rangen dREVERSE_RANGE:Returns vector range in reverse orderData AttributesExample:Consider the following signal:SIGNAL d:STD_LOGIC_VECTOR(7 DOWNTO 0);Then:dLOW=0,dHIGH=7,dLEFT=7,dRIGHT=0,dLENGTH=8,dRANGE=(7 downto 0),dREVERSE_RANGE=(0 to 7).Example:Consider the following sig

23、nal:SIGNAL x:STD_LOGIC_VECTOR(0 TO 7);Then all four LOOP statements below are synthesizable and equivalent.FOR i IN RANGE(0 TO 7)LOOP.FOR i IN xRANGE LOOP.FOR i IN RANGE(xLOW TO xHIGH)LOOP.FOR i IN RANGE(0 TO xLENGTH-1)LOOP.nLet us consider a signal s.Then:n sEVENT:Returns true when an event occurs

24、on sn sSTABLE:Returns true if no event has occurred on sn sACTIVE:Returns true if s=1n sQUIET:Returns true if no event has occurred during the time specifiedn sLAST_EVENT:Returns the time elapsed since last eventn sLAST_ACTIVE:Returns the time elapsed since last s=1n sLAST_VALUE:Returns the value of

25、 s before the last event;etc.Signal AttributesExample:All four assignments shown below are synthesizable and equivalent.They return TRUE when an event(a change)occurs on clk,AND if such event is upward(in other words,when a rising edge occurs on clk).IF(clkEVENT AND clk=1).-EVENT attribute used -with IFIF(NOT clkSTABLE AND clk=1).-STABLE attribute used -with IFWAIT UNTIL(clkEVENT AND clk=1).-EVENT attribute used -with WAITIF RISING_EDGE(clk).-call to a function