新编-TFT-LCD-工艺制程简介-精品课件.ppt

1、2009年年04月月21日日周刚09-4-19编写ContentsArray process Module ProcessCell Process TFT LCD 客户导向，团结协作 精益生产，精益管理q Team workTFT-LCDCOGRecipeOICSTKODFADIq TFT-LCD ENGLISH一一：Array Process q Organizationq Array Layout TFT ARRAY PROCESSCCITO pixel electrodeCross-section C-CSelect lineData lineStorage capacitorCCITO

2、 pixel electrodeCross-section C-CSelect lineData lineStorage capacitora-Si TFTTFT Structure Deposit and pattern gate metal Functions:Gate of TFT Select lines Bottom electrode of storage capacitor Metal options:Ti/Al/Ti Al/Mo Cr MoCCCross-section CCa-Si TFT array process step 1a-Si TFT array process

3、step 2 Deposition of SiN/a-Si/n+by PECVD,patterning of a-Si SiN is gate dielectric and storage capacitor dielectric Selective etch of a-Si SiN is not etchedCCSiNa-Si/n+a-Si TFT array process step 3 Deposition and patterning of source/drain metal Functions:Source and drain metal Data line metal Metal

4、 options Ti/Al/Ti or Ti/Al Cr Mo or Mo/Al Back etch of n+a-Si from channel areaCCa-Si TFT array process step 4 Deposition and patterning of passivation SiN by PECVD Function:Passivate TFTCCa-Si TFT array process step 5 Deposition and patterning of ITO Function:Pixel electrode Top electrode of storag

5、e capacitorCCITO pixel electrodeCross-section C-CSelect lineData lineStorage capacitorCCITO pixel electrodeCross-section C-CSelect lineData lineStorage capacitora-Si TFT TFT ARRAY PROCESS_PVD/CVDUsed for ITO(Indium Tin Oxide transparent conductor)and for metals(Al,Mo,Cr,etc.)Schematic diagram of DC

6、powered sputter deposition equipment(glow discharge)ground-V(DC)VacuumCathode shield-100-1000VPVD原理ACLSLoadlockT/CP/CP/CP/CP/CP/CPECVD(即等离子体增强化学气相沉积即等离子体增强化学气相沉积)工作原理工作原理:采用等离子辅助对化合物进行催化分解采用等离子辅助对化合物进行催化分解目的目的:利用等离子体辅助活化反应气体利用等离子体辅助活化反应气体,降低反应温度降低反应温度,改善薄膜质量改善薄膜质量PECVD原理LayerFeed gasMaterialTempFunc

7、tion3 LayerSiH4,N2,NH3A-SiNx320350Gate insulator SiH4,H2a-SiSemiconductorSiH4,PH3,H2n+a-SiContact layer at source and drain1 LayerSiH4,N2,NH3A-SiNx270290 passivation温度气体流量比(Si:H,N:H,Si:N)RFPressure Spacing(上下电极间距)影响成膜工艺的主要参数周刚09-4-19编写 M/A EUVMAINT EXT/COL4U/CU/CU/CU/C C/SSCRHP3HP3HP1HP3HP1COL1COL1

8、M/A DP DEVELOPEREXTPSPSEXT M/A HP2HP2I/FBUFCOL3TITLER/EE EXTEXTHP2COL2EXTPSPSPSPSOUTINOUTINOUT30600mm6000mmHeight:2450mm5585mm TFT ARRAY PROCESS_PHOTOSLIT COATEREXPOSURECANON MPA6000 JUMPstageNozzleSlit Coater&DPDPMPA6000 Exposure unitArrayCFTP&OL MarkOLTP TFT ARRAY PROCESS_WET TFT ARRAY PROCESS_DRY

9、Cassette stationL/LT/CP/CP/CP/CP/CDET原理利用Plasma将反应气体解离，ion轰击与radicals反应将Film移除，真空下进行RIE：指的是：指的是Reactive ion etching，即反应离子刻蚀，即反应离子刻蚀 目的 蚀刻终点检测。原理利用从蚀刻中开始到结束为止特定的波长的光强度的变化，检测出蚀刻的最合适的终点。plasma13.56 MHz検出器Optical fiberArray Tester将TFT Array Panel进行测试，如果有短路（SHORT),或是短路(OPEN),就将坐标点记录下来，传给Laser Repair（激光修复

10、机）修复之1.测量元件导通电流测量元件导通电流,ION2.测量元件截止电流测量元件截止电流,IOFF3.测量切入测量切入(CUT IN)电压电压VT4.测量电压电流曲线测量电压电流曲线TV CURVE电压电压V电流电流I切入電壓切入電壓IOFFIONTEG2022-8-3TAKE A BREAKTAKE A BREAKQUESTION AND ANSWER周刚09-4-19编写二二：Cell ProcessCFCFTFTTFTPI LinePI LineRubbing LineRubbing LineCFCFTFTTFTODF LineODF LineCELLCELLCFCFTFTTFTCEL

11、L工艺流程APR:Asahi Photosensitive ResinPI CoaterPI Coater要求特性RubbingRubbing 动作动作Spacer SprayShort DispenserSeal DispenserLC DispenserUV CUREAssemblyODF制成12ScriberZero level detect工作台运动方向及速度切割过程1.1.2.2.3.3.4.4.5.5.6.6.E-C-PLength Length GrindingGrindingWidth Width GrindingGrindingInInOutOutEdge Grind(Ski

12、p)CleanerPOL Attach侧面动作示意正面动作示意POL 周刚09-4-19编写三三：Module ProcessMODULE工艺流程图工艺流程图ACFFOG UV LINKCOGIC 邦定镜检AOI检测FOGACF 粘贴FOG 邦定镜检电测1封胶胶带粘贴补强UV固化组装副屏电测背光源检测背光源组装主副屏焊接背光源焊接主副屏组装外框组装外框焊接触摸屏组装触摸屏焊接保护胶带粘贴最终电测老化老化包装包装出货出货 JUMPModule Process FlowDriver Connection to GlassChip on Film(COF)or Chip on Glass(COG)ACFCOGCOG ProcessFPCFPC ProcessUVAging Conditions:50 deg.C2 hrsAging