数字设计基础双语课件(第10章).ppt

1、 10.Behavioral and Structural Descriptions 10.1 An example 10.2 The dataflow description10.3 Structural VHDL10.4 Processes10.5 Sequential and concurrent VHDL1 10.1 An example Example:a Four-bit adder sum=x+y;Describe a 4-bit adder in VHDL 1111110011101010100110110010100110000000Carry outSumCarry iny

2、x2 10.1 An example Circuit diagram 3 10.2 The dataflow descriptiona behavioral description of the full adder LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY fulladd IS PORT(x,y,cin:IN STD_LOGIC;sum,cout:OUT STD_LOGIC);END ENTITY fulladd;ARCHITECTURE simple OF fulladd ISBEGIN sum=cin XOR x XOR y;cout

3、=(x AND y)OR(cin AND x)OR(y AND cin);END ARCHITECTURE simple;4 10.2 The dataflow description1.Local signals Full adder circuit with the internal nodes n1,n2,n3,n4 are the internal nodes of the circuit 5 10.2 The dataflow descriptionARCHITECTURE number3 OF fulladd IS SIGNAL n1,n2,n3,n4:STD_LOGIC;BEGI

4、N n1=x XOR y;sum=cin XOR n1;n2=x AND y;n3=cin AND x;n4=y AND cin;cout=n2 OR n3 OR n4;END ARCHITECTURE number3;the VHDL description is changed toLocal signals n1,n2,n3 and n4 as part of the description 6 10.2 The dataflow description2.Concurrent processing ARCHITECTURE number3 OF fulladd IS SIGNAL n1

5、,n2,n3,n4:STD_LOGIC;BEGIN n1=x XOR y;sum=cin XOR n1;n2=x AND y;n3=cin AND x;n4=y AND cin;cout=n2 OR n3 OR n4;END ARCHITECTURE number3;Lets Consider the two descriptions（1）7 10.2 The dataflow descriptionARCHITECTURE number4 OF fulladd IS SIGNAL n1,n2,n3,n4:STD_LOGIC;BEGIN sum=cin XOR n1;cout=n2 OR n3

6、 OR n4;n1=x XOR y;n2=x AND y;n3=cin AND x;n4=y AND cin;END ARCHITECTURE number4;（2）8 10.2 The dataflow descriptionAlthough they are written in a different order,they do exactly the same thing.Unlike programming languages,VHDL normally monitors all statements at the same time,and executes a statement

7、 when one of its right hand side(RHS)values changes.This is called concurrent execution.Concurrent execution9 10.2 The dataflow description3.Dataflow VHDL In the jargon of VHDL,the style of coding that the outputs and inputs are related through Boolean or arithmetic operators and all statements oper

8、ate concurrently,is called dataflow.10 10.3 Structural VHDL1.The work library When designs are compiled they are placed into a library ready to be used by other designs.By default,the current working library is called work.When compiled,it is added to the work library.ARCHITECTURE simple OF fulladd

9、ISBEGIN sum=cin XOR x XOR y;cout x(0),y=y(0),cin=cin,sum=sum(0),cout=carry(1);This is called named association.With named association,the order doesnt matter.18 10.4 Processes 1.Sensitivity listsARCHITECTURE simple OF fulladd IS -1BEGIN -2 cout=(x AND y)OR(cin AND x)OR(y AND cin);-3 sum=cin XOR x XO

10、R y;-4END ARCHITECTURE simple;-5Statement 3 will run whenever a right hand side value changes.So it runs when x,y or cin changes.In the jargon of VHDL,statement 3 is sensitive to signals x,y,cin.Its sensitivity list is x,y,cin.A change in a signal is called an event on that signal.So statement 3 run

11、s whenever there is an event on a signal on its sensitivity list.19 10.4 Processes Statements 3 and 4 are concurrent,i.e.they are both active at the same time,and are triggered by an event on a signal on their sensitivity lists.2.The structure of a process PROCESS(sensitivity list)BEGIN Statement 1;

12、Statement 2;Statement 3;END PROCESS;20 10.4 Processes(1)The process waits until it is triggered by an event on one of the signals in its sensitivity list.(2)When it is triggered it executes each of the statements in its body sequentially.(3)During execution of the process,all signal values are froze

13、n and are not updated or changed in any way during the execution of the process(4)The LHS signals all receive their new value after the process has suspended its execution.21 10.4 Processes VHDL description in processes ARCHITECTURE all_in_one OF fulladd IS BEGIN PROCESS(x,y,cin)BEGIN cout=(x AND y)

14、OR(cin AND x)OR(y AND cin);sum=cin XOR x XOR y;END PROCESS;END ARCHITECTURE all_in_one;22 10.4 Processes 3.The WAIT statement Instead of using a sensitivity list,we can the timing of execution of a process by using a WAIT statement.ARCHITECTURE using_wait OF fulladd IS BEGIN PROCESS BEGIN WAIT ON x,

15、y,cin;cout=(x AND y)OR(cin AND x)OR(y AND cin);sum=cin XOR x XOR y;END PROCESS;END ARCHITECTURE using_wait;23 10.5 Sequential and concurrent VHDL1.Sequential and concurrent conditionals（1）Sequential IF blockIF condition_1 THEN sequence of statements;ELSIF condition_2 THEN sequence of statements;ELSE

16、 sequence of statements;END IF;24 10.5 Sequential and concurrent VHDL（2）Concurrent WHEN statement a=value1 WHEN condition1 ELSE value2 WHEN conditon2 ELSE value3;25 10.5 Sequential and concurrent VHDL2.Sequential and concurrent selectionENTITY declaration a 4-input multiplexer LIBRARY ieee;USE ieee.

17、std_logic_1164.all;ENTITY mux4to1 IS PORT(address:IN STD_LOGIC_VECTOR(1 DOWNTO 0);data:IN STD_LOGIC_VECTOR(3 DOWNTO 0);y:out STD_LOGIC);END mux4to1;26 10.5 Sequential and concurrent VHDLThe operation of selecting one of the data lines to the output y depending on the value of address is accomplished

18、 in concurrent VHDL using a SELECT statement:ARCHITECTURE concurrent OF mux4to1 ISBEGINWITH address SELECT y=data(3)WHEN 11,data(2)WHEN 10,data(1)WHEN 01,data(0)WHEN OTHERS;END ARCHITECTURE concurrent;The OTHERS choice catches all other values for address that do not match any of the values explicitly listed.27