数字设计基础双语课件(第12章).ppt

1、 12.Describe sequential systems in VHDL 12.1 Defining clocks,flip-flops and registers 12.2 Register Transfer Level (RTL)Coding12.3 Sequential logic 1 12.1 Defining clocks,flip-flops®isters 1.Defining a clock signal PROCESSBEGIN clock=0;WAIT FOR 10 NS;clock=1WAIT FOR 10 NS;END PROCESS;There are ma

2、ny ways to define a clock.For example:Simulation waveform 2 12.1 Defining clocks,flip-flops®isters 2.The D-type flip-flopLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dff IS PORT(d,clock:IN STD_LOGIC;Q:OUT STD_LOGIC);END ENTITY dff;ARCHITECTURE correct OF dff ISBEGIN PROCESS(clock)BEGIN IF(risi

3、ng_edge(clock)THEN q=d;END IF;END PROCESS;END ARCHITECTURE correct;3 12.1 Defining clocks,flip-flops®isters 3.The D-type flip-flop with reset If the Reset is synchronous,then it is ignored until the rising edge of the clock.When the rising edge comes,if Reset=1 then q goes to 0.If Reset=0,then th

4、e flip-flop exhibits normal behavior,i.e.q=d.（1）If the Reset is synchronous4 12.1 Defining clocks,flip-flops®isters LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;-D-type flip-flopENTITY dff IS PORT(d :IN STD_LOGIC;-Data input clock:IN STD_LOGIC;-Clock input reset:IN STD_LOGIC;-Reset input Q :OUT STD_L

5、OGIC);-OutputEND ENTITY dff;ENTITY definition 5 12.1 Defining clocks,flip-flops®isters ARCHITECTURE synch_reset OF dff ISBEGIN PROCESS(clock)BEGIN IF(rising_edge(clock)THEN IF(reset=1)THEN q=0;ELSE q=d;END IF;END IF;END PROCESS;END ARCHITECTURE synch_reset;Architecture declaration6 12.1 Defining

6、clocks,flip-flops®isters If the Reset is asynchronous,then it takes immediate effect,no matter what the clock is doing.This means that the flip-flop is always sensitive to its Reset input.（2）If the Reset is asynchronous7 12.1 Defining clocks,flip-flops®isters ARCHITECTURE asynch_reset OF dff I

7、SBEGIN PROCESS(clock,reset)BEGIN IF(reset=1)THEN q=0;ELSIF(rising_edge(clock)THEN q=d;END IF;END PROCESS;END ARCHITECTURE asynch_reset;Architecture declaration should be:8 12.2 Register Transfer Level Coding1.VHDL description of a registered adderARCHITECTURE behavioral OF adder ISBEGIN sum=a+b;END

8、ARCHITECTURE behavioral;Behavioral description9 12.2 Register Transfer Level CodingAn obvious way to describe the adder with registered output is to instantiate 4 flip-flops at the output:ARCHITECTURE registered OF adder ISBEGIN sum sum(0),clock=clock,q=reg_sum(0);g2:ENTITY work.dff(correct)PORT MAP

9、(d=sum(1),clock=clock,q=reg_sum(1);g3:ENTITY work.dff(correct)PORT MAP(d=sum(2),clock=clock,q=reg_sum(2);g4:ENTITY work.dff(correct)PORT MAP(d=sum(3),clock=clock,q=reg_sum(3);END ARCHITECTURE registered;10 12.2 Register Transfer Level Coding2.Register Transfer Level VHDLIf we want a reset signal,tha

10、t can asynchronously reset the adder output to zero,the code should be:ARCHITECTURE rtl2 OF adder IS BEGIN PROCESS(clock,reset)BEGIN IF(reset=1)THEN reg_sum 0);ELSIF(rising_edge(clock)THEN reg_sum=a+b;end if;END PROCESS;END ARCHITECTURE rtl2;11 12.2 Register Transfer Level CodingThis style of coding

11、 is called register transfer level coding.We are using assignments to signals,but wrapping them up in processes triggered by the clock(and reset signal)in order to make it clear on what clock cycle the outputs should assume their values.12 12.2 Register Transfer Level Coding3.VHDL variables A VHDL v

12、ariable can only exist inside a process,and will assume its new value immediately whenever an assignment occurs.Like c and f in the following circuit.13 12.2 Register Transfer Level CodingARCHITECTURE fig12-10 OF adder ISBEGIN PROCESS(clock)VARIABLE e,f:SIGNED(31 DOWNTO 0);BEGIN IF(rising_edge(clock

13、)THEN c:=a+b;f:=d+e;sum=c+f;END IF;END PROCESS;END ARCHITECTURE fig12-10;Code listing using variables 14 12.3 Sequential logic 000001010011100101110111A Binary up-counterState diagram LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY counter IS PORT(clock:IN STD_LOGIC;count:OUT UNSIGNED(2 DOWNTO 0);END ENTITY counter;VHDL code 15