数字设计课件-第6章-组合逻辑设计实践2.ppt

1、22.7.211Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.22.7.21chapter 62本章重点n具备一定功能的通用组合逻辑电路的设计方法及实例n掌握常用的MSI的使用方法及功能扩展n掌握译码器、MUX实现组合逻辑功能的方法n能分析、设计由MSI构建的电路22.7.21chapter 636.1 Documentation Standard1.Signal Names and Active Leve

2、lsMost signals(signal name)have active level.active high active lowNaming convention surffix“_L”attaching to signal name represent active low level.Like,EN_L、READY_L In logic relation,EN_L=EN，READY_L=READY。22.7.21chapter 642.Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bub

3、bleActive lowENENDinstartDoutflgstartDinDoutflgActive hign22.7.21chapter 65Exp2：EN=1(active high),data can be transferredEN=0(active low),data can be transferredENCLKEN_LCLK22.7.21chapter 663.bubble-to-bubble logic designMake the logic circuit easier to understand.Exp：Not matchNot matchABSELDATAABAS

4、ELDATAmatchmatch22.7.21chapter 676.3 Combinational PLDs1.Programmable logic arrays(PLA)two level“ANDOR”device.Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms:ninputs moutputs pproduct terms22.7.21chapter 6843 with 6 product termsAND array22.7.21chapte

5、r 6922.7.21chapter 6102.Programmable Array Logic DevicesFixed OR array，programmable AND arrayBidirectional input/output pins，熔丝型，熔丝型PAL16L8，Output enable22.7.21chapter 6113.Generic Array Logic Devices（GAL）an innovation of the PAL;can be erased and reprogrammed;22.7.21chapter 6126.4 DecodernAn import

6、ant type of combinational circuit.input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit22.7.21chapter 6131、bianry decodersninput code：n-bitnoutput code：2n-bit 2-4 decoder（2-22）I1I0Y3Y2Y1Y0truth table：？：？Yi：？：？I1I0Y3 Y2 Y1 Y0000001010010100100111000Yi=miY0=I1I0Y

7、1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.22.7.21chapter 614n2-4 decoder with enable inputYi=EN miENI1I0Y3Y2Y1Y00 00001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder22.7.21chapter 615（2）74139,dual 2-4 decoderInput code：B（MSB）A（LSB）Also be called address input.O

8、utput code：Y3_LY0_LEN 22.7.21chapter 616（3）74138,3-8 decoderuEnable inputEN=G1G2A_LG2B_LuInput code：C（MSB）、）、B、AuOutput code：Y0_L Y7_LuYi_L=（ENmi）Y0_LY1_LY2_LY3_L Y4_L Y5_L Y6_L Y7_LG1G2A_LG2B_LEN22.7.21chapter 617ENmsblsb22.7.21chapter 6182、realizing combinational circuits with decodernreview：canon

9、ical sumnDecoder output：Yi_L=(ENmi)when EN=1，Yi_L=mi=Mi add an NAND gate to the decoders output.Exp:(1)F=AB（0、3）F=AB+ABEnable asserted22.7.21chapter 619（2）if a 3-bit number XYZ is odd number，then ODD output 1，else output 0.realize the function with decoder and gates.solution：F=？F=XYZ（1，3，5，7）22.7.21

10、chapter 620（3）F=XYZ（0、1、5）解：解：22.7.21chapter 6213.Cascading binary decodersnHow to construct a 4-16、5-32 decoder？use multiple 2-4 or 3-8 decoders to cascade.nPS.：confirm the number of decoders according to the input and output bits.only one chip works in each decoding operation.22.7.21chapter 622Exp

11、：a 4-16 decoderInputs:4-bit N3、N2、N1、N0。Outputs:16-bit DEC15_LDEC0_LNeed 2 3-8 decoders.Use the MSB of the inputs as chip-select bit.000000010111100010011111N3 N2 N1 N0N3 N2 N1 N022.7.21chapter 623Chip selecting22.7.21chapter 624nExp：4-bit prime-number detector.Realizing it with 74138 and some gates

12、.N3N2N1N0U174HC138D_6VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U274HC138D_6VY015Y114Y213Y312Y411Y510Y69Y77A1B2C3G16G2A4G2B5U374HC30D_6VR1 1kR21kVCC5VGNDGNDF22.7.21chapter 6254、7-segment decoderClassify of 7-seg displayer：in materials:LED（发光二极管）（发光二极管）LCD（液晶）（液晶）In working mode:common-cathode(共

13、阴极共阴极)common-anode(共阳极共阳极)afbcegddpabcdedpfggndgnd22.7.21chapter 626 7-segment decoder transform the input BCD code to 7-segment displaying code.devices：7446A、74LS47（驱动共阳）（驱动共阳）74LS48、74LS49（驱动共阴）（驱动共阴）00001001 are useful input codes.10101111 are unused BCD code.22.7.21chapter 627U1A5B1C2D4OA11OD8OE

14、6OF13OC9OB10OG12BI3U2A B C D E F GCKHGNDVCCR1R6R7R8R9R10 R1174LS4922.7.21chapter 6285、BCD decoder（二（二十进制译码器）十进制译码器）Inputs:BCDY0Y9BCD decoderOutput:1-out-of 10 code74HC4222.7.21chapter 6295.5 Encoder1、binary encoder inputs:1-out-of-2n codeI0I1Im(m=2n-1)output:n-bitY0Y1Yn-1binary encoder22.7.21chapter

15、 6308-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:active high22.7.21chapter 631Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7 Each input port has its corresponding output code.22.7.21chapter 6322、Priority Encode

16、r if multiple inputs are asserted,how to deal with?solution：assign priority to each input from high to low.let I7 highest priority and decrease from I6 down to I0 A2,A1,A0encode output IDLEwhen no input is asserted,IDLE=122.7.21chapter 633inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE111100111000011010000110

17、0000001011000000101000000001001000000001000000000000000122.7.21chapter 634Logic expressions for priority encoderH7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I3I4I5I6I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7)=I0I1I2I3I4I5I6I7Expressions for each asserted input in the truth table of p

18、riority encoderOutput code expressions 22.7.21chapter 6353、74148 Priority Encoder EI_L：Enable Input.I7_LI0_L：encode input，I7_L has highest priority.A2_LA0_L：encode output GS_L：GS_L=0 when one or more of the request inputs are asserted.EO_L：enable output,EO_L=0 when all of the request inputs are nega

19、tive and EI_L=0.高高低低优先级优先级22.7.21chapter 636n74148真值表真值表22.7.21chapter 6374、cascading priority encoderproblem：how to construct 16-4、32-5 priority encoder？Connecting multiple 8-3 endoder.nnote：make sure the needed number of chips according to the inputs.need to redesign the output circuit that could

20、produce the correct encoding output.22.7.21chapter 638n16-4 priority encoder:use two 74148 U1、U2，(1)U1:input E15_LE8_L;U2:input E7_LE0_L;E15_L is the highest priority,(2)output:A3_LA0_L，active low;(3)When one or more inputs is asserted，GS0_L=0；and A3_LA0_L=1111.22.7.21chapter 63916-4 priority encode

21、rU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_LEN13_LEN12_LEN11_LEN10_LEN9_LEN8_LEN7_LEN6_LEN5_LEN4_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_L22.7.21chapter 640n思考：若需要编码输出、思考：若需要编码输出、GS0为

22、高电平有效，如何为高电平有效，如何修改电路输出结构？修改电路输出结构？nP.413 figure 6-49 shows the 32-5 priority encoders strcture,.22.7.21chapter 6416.6 Three-state Devices1、three-state buffers22.7.21chapter 642Enable means:the buffer output normal logic 0、1 when EN is asserted；the buffer output Hi-Z when EN is negated.22.7.21chapte

23、r 643lApplication data address of data source22.7.21chapter 644lIssues in application TPLZ、TPHZ：time that takes from normal logic into Hi-Z;TPZL、TPZH：time that takes from Hi-Z into normal logic;generally，TPLZ、TPHZ TPZL、TPZH But to confirm the correction in application,a control logic is adopted.22.7

24、.21chapter 64574138的的相关相关引脚引脚信号信号 截止时间截止时间（停滞时间）（停滞时间）22.7.21chapter 646课堂练习课堂练习n试设计一个电路，当控制信号试设计一个电路，当控制信号M=1时，电路为时，电路为“判一致判一致”电路，即当三个输入变量取值全部相电路，即当三个输入变量取值全部相同时输入为同时输入为1；当控制信号；当控制信号M=0时，电路为时，电路为“多数多数表决表决”电路，即输出等于输入变量中占多数的取电路，即输出等于输入变量中占多数的取值。请写出最简表达式。（注：至少要写出卡诺值。请写出最简表达式。（注：至少要写出卡诺图，三变量为图，三变量为X、Y、

25、Z）22.7.21chapter 6476.7 Multiplexer2-to-1 MUXABSELYY=SELA+SELBS=0，Y=AS=1，Y=BABS=0Y=AABS=1Y=BLogic circuit22.7.21chapter 648又称数据选择器，简称又称数据选择器，简称MUXOutput:enableselect n data source data output10(1)njjjiYEN m iDib gg n2s mj：SELj minterm1、基本结构：、基本结构：22.7.21chapter 649Let b=1,10njjjYEN m DggD0D1DjDn-1SE

26、LEN22.7.21chapter 650Exp:4-to-1 MUXABCDS1S001101234outputCS0S1output00A01B10C11D22.7.21chapter 6512、MSI MUX（1）8-to-1 MUX，74151EN_LaddressY_LY22.7.21chapter 65270jjjYEN m Dgg返回返回22.7.21chapter 653（2）4-bit,2 input MUX，7415722.7.21chapter 654（3）2 bit,4 input MUX，74 153inputoutput1G_L2G_LBA1Y2Y00001C02C

27、000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311001G_L2G_L22.7.21chapter 6553、Expanding MUXsExp1：use 74151 to realize a 16-to-1 MUX,some gates can be used if necessary.Chips needed：according to the 16 inputs,2 74151 chips.output：combine two chips outp

28、uts into one output.22.7.21chapter 656The MSB(A3)of input act as the chip-select bit.22.7.21chapter 657Exp2：用：用74153实现实现4输入，输入，4位位MUX，。，。设设4路输入分别是：路输入分别是：1D3.0、2D3.0、3D3.0、4D3.0；4位输出是：位输出是：Dout3.0 输入选择：输入选择：S1、S0解：无需外加门，只需要合理安排输入、输出数据解：无需外加门，只需要合理安排输入、输出数据端口即可。端口即可。22.7.21chapter 658S1S022.7.21chapt

29、er 6594、用、用MUX实现组合逻辑函数的标准和实现组合逻辑函数的标准和 multiple input,1 bit MUX,the output：when EN is asserted：the canonical sum form.10njjjYEN m Dgg10njjjYm Dg74151的内部电路的内部电路mj:minterm of the select(address)inputs.22.7.21chapter 660 MUX的数据输入端与真值表的每行输出对应，的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即的地址选择端作为最小项产生器，即 真值表：真值表

30、：输出值输出值输入变量输入变量 MUX：数据输入端数据输入端地址端地址端Exp1：a circuit output 1 when its 3-bit input can be divided by 3.construct the circuit by using 74151.So：F=XYZ（？）（？）and circuit？按最小项编号顺序按最小项编号顺序变量与选择端对应变量与选择端对应22.7.21chapter 661n例例1的电路的电路XYZFU1W6D04D13D22D31D415D514D613D712S011S29S110Y5G7VCCGNDR122.7.21chapter 66

31、2例例2：若例：若例1中输入数为中输入数为4位二进制数，如何实现？位二进制数，如何实现？解解1：用：用16输入，输入，1位的位的MUX来实现，选用来实现，选用74150。F=WXYZ（0，3，6，9，12，15）解解2：仍选用：仍选用74151，先对所求函数的卡诺图做，先对所求函数的卡诺图做降维处理。降维处理。l预备知识：预备知识：卡诺图的降维卡诺图的降维 用一个用一个n变量的卡诺图来处理变量的卡诺图来处理m变量的函数变量的函数（nB)F(A=B)F(AB=ABFABFABFA=BFAB=(A1B1)+(A1=B1)(A0B0)=A1B1+(AB+AB)(A1B1)FA=B=(A1=B1)(A

32、0=B0)FAB=(A1B1)+(A1=B1)(A0BFA=BFABA1B11A1=B1A0B01A1=B1A0=B01Pseudo-logic22.7.21chapter 6924.Standard MSI magnitude comparator7485:4-bituMagnitude input:A3.0,B3.0uCascading input：ALBI、AEBI、AGBI，which are used to expanding comparator.uoutput：ALBO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(ABFA=BF

33、ABFA=BFABX11.8Y11.8X7.4Y7.4X3.0Y3.022.7.21chapter 695Class exerciseABCDFDAADCDCABJudge whether the following circuit has static hazard or not,if static hazard exist,please point it and eliminate by using K-map.Then write the hazardless minimal sum.22.7.21chapter 6966.10 Adders、Subtractors and ALUnUs

34、ed to do binary addition and subtraction1.Half adders and full adders（1）half addersXYHSCO0000011010101101half sum：HS=X Ycarry-out：CO=XYXYHSCO22.7.21chapter 697（2）full addersCINXYSCO0000000110010100110110010101011100111111sum：S=X Y CINcarry：CO=XY+CINX+CINY22.7.21chapter 6982、ripple addersnUse 1-bit f

35、ull adder as a module to construct n-bit ripple adder.XYCINCOSX0Y0S0C0C1XYCINCOSX1Y1S1XYCOSXn-1 Yn-1Sn-1C2Cn电路简单，扩展方便，但运算速度慢电路简单，扩展方便，但运算速度慢22.7.21chapter 6993、carry-lookahead addersParallel addersnissues：how to get the carry information early?nsolution：carry-lookahead（1）definition：carry generating

36、variable：gi=xiyi carry propagating variable：pi=xi+yi the Ci+1 carry-out：Ci+1=gi+piCi22.7.21chapter 6100Ci+1=gi+pi(gi-1+pi-1(g0+p0C0)C0=0，Ci is relative to addends only and just three level delay,which to reduce the computation time.（2 2）structureuSi=Xi Yi CiuCi+1=gi+piCiSiXiXi-1X0YiYi-1Y0CiC0两级与或式两级

37、与或式22.7.21chapter 6101（3）MSI adders74283，4-bit carry-lookahead adders加法器的级联（加法器的级联（P.482图图6-89）22.7.21chapter 61024、subtractornFull subtractorD=X Y BINBO=BINY+BINX+XYBINXYDBO0000000111010100110010011101011100011111XYBODBIN22.7.21chapter 6103nIn algorithm,subtraction can be operated by using addition.X-Y=X+(Y)2s=X+(Y)1s+1nSo circuit can be manipulated：D=X Y BIN BO=(BINX+BINY+XY)DBINBOsubtractor22.7.21chapter 61045、MSI arithmetic and logic unitsnperform a number of different arithmetic and logical operations.ABFSELMCINCOGPA=B