第六章VerilogHDL高级程序设计举例课件.ppt

1、第六章第六章 Verilog HDL高级程序高级程序设计举例设计举例2022-11-141Microelectronics School Xidian University 6.1数字电路系统设计的层次化描述方法数字电路系统设计的层次化描述方法Bottom-Up:11/14/20222Microelectronics School Xidian University 串行加法器:一个四位串行加法器由4个全加器构成。全加器是串行加法器的子模块，而全加器是由基本的逻辑门构成，这些基本的逻辑门就是所说的叶子模块。这个设计中运用叶子模块（基本逻辑门）搭建成子模块（全加器），再用子模块搭建成所需要的电路

2、（串行加法器）。显然，Bottom-Up的设计方法没有明显的规律可循，主要依靠设计者的实践经验和熟练的设计技巧，用逐步试探的方法最后设计出一个完整的数字系统。系统的各项性能指标只有在系统构成后才能分析测试。此种设计方法常用于原理图的设计中，相比于其它方法此种方法对于实现各个子模块电路所需的时间较短。11/14/20223Microelectronics School Xidian University Top-Down:11/14/20224Microelectronics School Xidian University 使用Top-Down设计方法对一个典型cpu进行设计：11/14/20

3、225Microelectronics School Xidian University 向量点积乘法器：采用模块层次化设计方法，设计4维向量点积乘法器，其中向量a=（a1，a2，a3，a4）；b=（b1，b2，b3，b4）。点积乘法规则为：11/14/20226Microelectronics School Xidian University 1 1223 344+a baba ba ba b 11/14/20227Microelectronics School Xidian University Verilog HDL程序代码为：module vector(a1,a2,a3,a4,b1,b

4、2,b3,b4,out);input 3:0 a1,a2,a3,a4,b1,b2,b3,b4;output 9:0 out;wire 7:0 out1,out2,out3,out4;wire 8:0 out5,out6;wire 9:0 out;mul_addtree U1(.x(a1),.y(b1),.out(out1);mul_addtree U2(.x(a2),.y(b2),.out(out2);mul_addtree U3(.x(a3),.y(b3),.out(out3);mul_addtree U4(.x(a4),.y(b4),.out(out4);add#(8)U5(.a(out1

5、),.b(out2),.out(out5);add#(8)U6(.a(out3),.b(out4),.out(out6);add#(9)U7(.a(out5),.b(out6),.out(out);endmodule/addermodule add(a,b,out);parameter size=8;input size-1:0 a,b;output size:0 out;assign out=a+b;endmodule/Multipliermodule mul_addtree(mul_a,mul_b,mul_out);input 3:0 mul_a,mul_b;/IO declaration

6、output 7:0 mul_out;wire 3:0 mul_out;/Wire declaration wire 3:0 stored0,stored1,stored2,stored3;wire 3:0 add01,add23;assign stored3=mul_b3?1b0,mul_a,3b0:8b0;/Logic design assign stored2=mul_b2?2b0,mul_a,2b0:8b0;assign stored1=mul_b1?3b0,mul_a,1b0:8b0;assign stored0=mul_b0?4b0,mul_a:8b0;assign add01=s

7、tored1+stored0;assign add23=stored3+stored2;assign mul_out=add01+add23;endmodule6.2典型电路设计典型电路设计 6.2.1加法器树乘法器加法器树乘法器的设计思想是“移位后加”，并且加法运算采用加法器树的形式。乘法运算的过程是，被乘数与乘数的每一位相乘并且乘以相应的权值，最后将所得的结果相加，便得到了最终的乘法结果。例：下图是一个4位的乘法器结构，用Verilog HDL设计一个加法器树4位乘法器11/14/20228Microelectronics School Xidian University 11/14/20

8、229Microelectronics School Xidian University module mul_addtree(mul_a,mul_b,mul_out);input 3:0 mul_a,mul_b;/IO declarationoutput 7:0 mul_out;wire 7:0 mul_out;/Wire declaration wire 7:0 stored0,stored1,stored2,stored3;wire 7:0 add01,add23;assign stored3=mul_b3?1b0,mul_a,3b0:8b0;/Logic designassign st

9、ored2=mul_b2?2b0,mul_a,2b0:8b0;assign stored1=mul_b1?3b0,mul_a,1b0:8b0;assign stored0=mul_b0?4b0,mul_a:8b0;assign add01=stored1+stored0;assign add23=stored3+stored2;assign mul_out=add01+add23;endmodulemodule mult_addtree_tb;reg 3:0mult_a;reg 3:0mult_b;wire 7:0mult_out;/module instancemul_addtree U1(

10、.mul_a(mult_a),.mul_b(mult_b),.mul_out(mult_out);initial /Stimuli signal begin mult_a=0;mult_b=0;repeat(9)begin#20 mult_a=mult_a+1;mult_b=mult_b+1;end end endmodule流水线结构流水线结构例：下图是一个4位的乘法器结构，用Verilog HDL设计一个两级流水线加法器树4位乘法器。两级流水线加法器树4位乘法器结构如图所示，通过在第一级与第二级、第二级与第三级加法器之间插入D触发器组，可以实现两级流水线设计。11/14/202210Mic

11、roelectronics School Xidian University 11/14/202211Microelectronics School Xidian University module mul_addtree_2_stage(clk,clr,mul_a,mul_b,mul_out);input clk,clr;input 3:0 mul_a,mul_b;/IO declaration output 7:0 mul_out;reg 7:0 add_tmp_1,add_tmp_2,mul_out;wire 7:0 stored0,stored1,stored2,stored3;ass

12、ign stored3=mul_b3?1b0,mul_a,3b0:8b0;/Logic designassign stored2=mul_b2?2b0,mul_a,2b0:8b0;assign stored1=mul_b1?3b0,mul_a,1b0:8b0;assign stored0=mul_b0?4b0,mul_a:8b0;always(posedge clk or negedge clr)/Timing controlbegin if(!clr)begin add_tmp_1=8b0000_0000;add_tmp_2=8b0000_0000;mul_out=8b0000_0000;e

13、nd else begin add_tmp_1=stored3+stored2;add_tmp_2=stored1+stored0;mul_out=add_tmp_1+add_tmp_2;end endendmodule11/14/202212Microelectronics School Xidian University module mult_addtree_2_stag_tb;reg clk,clr;reg 3:0mult_a,mult_b;wire 7:0mult_out;mul_addtree_2_stage U1(.mul_a(mult_a),.mul_b(mult_b),.mu

14、l_out(mult_out),.clk(clk),.clr(clr);initial begin clk=0;clr=0;mult_a=1;mult_b=1;#5 clr=1;end always#10 clk=clk;initial begin repeat(5)begin#20 mult_a=mult_a+1;mult_b=mult_b+1;end end endmodule6.2.2 Wallace 树乘法器树乘法器Wallace树乘法器运算原理如下图所示，其中FA为全加器HA为半加器。其基本原理是，加法从数据最密集的地方开始，不断地反复使用全加器半加器来覆盖“树”。这一级全加器是一个

15、3输入2输出的器件，因此全加器又称为3-2压缩器。通过全加器将树的深度不断缩减，最终缩减为一个深度为2的树。最后一级则采用一个简单的两输入加法器组成。11/14/202213Microelectronics School Xidian University 11/14/202214Microelectronics School Xidian University module wallace(x,y,out);parameter size=4;/Define parameters input size-1:0 x,y;output 2*size-1:0 out;/IO declaration

16、wire size*size-1:0 a;wire 1:0 b0,b1,c0,c1,c2,c3;/Wire declaration wire 5:0 add_a,add_b;wire 6:0 add_out;wire 2*size-1:0 out;11/14/202215Microelectronics School Xidian University assign a=x3,x3,x2,x2,x1,x3,x1,x0,x3,x2,x1,x0,x2,x1,x0,x0&y3,y2,y3,y2,y3,y1,y2,y3,y0,y1,y1,y2,y0,y0,y1,y0;/Pre part multipl

17、ierhadd U1(.x(a8),.y(a9),.out(b0);/2 input half adder hadd U2(.x(a11),.y(a12),.out(b1);hadd U3(.x(a4),.y(a5),.out(c0);fadd U4(.x(a6),.y(a7),.z(b00),.out(c1);/3 input full adder fadd U5(.x(a13),.y(a14),.z(b01),.out(c2);fadd U6(.x(b10),.y(a10),.z(b11),.out(c3);assign add_a=c31,c21,c11,c01,a3,a1;/adder

18、 assign add_b=a15,c30,c20,c10,c00,a2;assign add_out=add_a+add_b;assign out=add_out,a0;endmodulemodule fadd(x,y,z,out);output 1:0out;input x,y,z;assign out=x+y+z;endmodulemodule hadd(x,y,out);output 1:0out;input x,y;assign out=x+y;endmodule11/14/202216Microelectronics School Xidian University module

19、wallace_tb;reg 3:0 x,y;wire 7:0 out;wallace m(.x(x),.y(y),.out(out);/module instance initial /Stimuli signal begin x=3;y=4;#20 x=2;y=3;#20 x=6;y=8;end endmodule 6.2.3复数乘法器复数乘法的算法是：设复数 ，则复数乘法结果复数乘法器的电路结构如下图所示。将复数x的实部与复数y的实部相乘，减去x的虚部与y的虚部相乘，得到输出结果的实部。将x的实部与y的虚部相乘，加上x的虚部与y的实部相乘，得到输出结果的虚部。11/14/202217Mi

20、croelectronics School Xidian University,xabiycdi()()()()xyabi cdiacbdi adbc11/14/202218Microelectronics School Xidian University module complex(a,b,c,d,out_real,out_im);input 3:0a,b,c,d;output 8:0 out_real,out_im;wire 7:0 sub1,sub2,add1,add2;wallace U1(.x(a),.y(c),.out(sub1);wallace U2(.x(b),.y(d),.

21、out(sub2);wallace U3(.x(a),.y(d),.out(add1);wallace U4(.x(b),.y(c),.out(add2);assignout_real=sub1-sub2;assign out_im=add1+add2;endmodulemodule complex_tb;reg 3:0 a,b,c,d;wire 8:0 out_real;wire 8:0 out_im;complex U1(.a(a),.b(b),.c(c),.d(d),.out_real(out_real),.out_im(out_im);initial begin a=2;b=2;c=5

22、;d=4;#10 a=4;b=3;c=2;d=1;#10 a=3;b=2;c=3;d=4;end endmodule6.2.4 FIR滤波器设计有限冲激响应（FIR）滤波器就是一种常用的数字滤波器，采用对已输入样值的加权和来形成它的输出。其系统函数为其中z-1表示延时一个时钟周期，z-2表示延时两个时钟周期。对于输入序列Xn的FIR滤波器可用下图所示的结构示意图来表示，其中Xn是输入数据流。各级的输入连接和输出连接被称为抽头，并且系数（b0,b1,bn）被称为抽头系数。一个M阶的FIR滤波器将会有M+1个抽头。通过移位寄存器用每个时钟边沿n（时间下标）处的数据流采样值乘以抽头系数，并将它们加起

23、来形成输出Yn。11/14/202219Microelectronics School Xidian University 11/14/202220Microelectronics School Xidian University module FIR(Data_out,Data_in,clock,reset);output 9:0 Data_out;input 3:0 Data_in;input clock,reset;wire 9:0 Data_out;wire 3:0 samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,

24、samples_6,samples_7,samples_8;shift_register U1(.Data_in(Data_in),.clock(clock),.reset(reset),.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8);caculato

25、r U2(.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8),.Data_out(Data_out);endmodule11/14/202221Microelectronics School Xidian University module shift_r

26、egister(Data_in,clock,reset,samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8);input 3:0 Data_in;input clock,reset;output 3:0 samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;reg 3:0 samples_0,samples_1,samples_2,sample

27、s_3,samples_4,samples_5,samples_6,samples_7,samples_8;always(posedge clock or negedge reset)begin if(reset)begin samples_0=4b0;samples_1=4b0;samples_2=4b0;samples_3=4b0;samples_4=4b0;samples_5=4b0;samples_6=4b0;samples_7=4b0;samples_8=4b0;end11/14/202222Microelectronics School Xidian University else

28、 begin samples_0=Data_in;samples_1=samples_0;samples_2=samples_1;samples_3=samples_2;samples_4=samples_3;samples_5=samples_4;samples_6=samples_5;samples_7=samples_6;samples_8=samples_7;end end endmodulemodule caculator(samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,s

29、amples_8,Data_out);input 3:0 samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;output 9:0 Data_out;wire 9:0 Data_out;wire 3:0 out_tmp_1,out_tmp_2,out_tmp_3,out_tmp_4,out_tmp_5;wire 7:0 out1,out2,out3,out4,out5;11/14/202223Microelectronics School Xidian Univers

30、ity parameter b0=4b0010;parameter b1=4b0011;parameter b2=4b0110;parameter b3=4b1010;parameter b4=4b1100;mul_addtree U1(.mul_a(b0),.mul_b(out_tmp_1),.mul_out(out1);mul_addtree U2(.mul_a(b1),.mul_b(out_tmp_2),.mul_out(out2);mul_addtree U3(.mul_a(b2),.mul_b(out_tmp_3),.mul_out(out3);mul_addtree U4(.mul

31、_a(b3),.mul_b(out_tmp_4),.mul_out(out4);mul_addtree U5(.mul_a(b4),.mul_b(samples_4),.mul_out(out5);assign out_tmp_1=samples_0+samples_8;assign out_tmp_2=samples_1+samples_7;assign out_tmp_3=samples_2+samples_6;assign out_tmp_4=samples_3+samples_5;assign Data_out=out1+out2+out3+out4+out5;endmodule11/

32、14/202224Microelectronics School Xidian University module FIR_tb;reg clock,reset;reg 3:0 Data_in;wire 9:0 Data_out;FIRU1(.Data_out(Data_out),.Data_in(Data_in),.clock(clock),.reset(reset);initial begin Data_in=0;clock=0;reset=1;#10 reset=0;end always begin#5 clock=clock;#5 Data_in=Data_in+1;endendmod

33、ule6.2.5片内存储器的设计片内存储器的设计（1）RAM的Verilog HDL描述RAM是随机存储器，存储单元的内容可按需随意取出或存入。这种存储器在断电后将丢失掉所有数据，一般用来存储一些短时间内使用的程序和数据。其内部结构如下图所示：11/14/202225Microelectronics School Xidian University 例：用例：用Verilog HDL设计深度为设计深度为8，位宽为，位宽为8的单端口的单端口RAM。单口单口RAM，只有一套地址总线，读操作和写操作是分开的，只有一套地址总线，读操作和写操作是分开的。11/14/202226Microelectron

34、ics School Xidian University module ram_single(clk,addm,cs_n,we_n,din,dout);input clk;/clock signal input 2:0 addm;/address signalinput cs_n;/chip select signalinput we_n;/write enable signalinput 7:0 din;/input dataoutput7:0 dout;/output datareg 7:0 dout;reg 7:0 raml 7:0;/8*8 bites registeralways(p

35、osedge clk)beginif(cs_n)dout=8bzzzz_zzzz;else if(we_n)/read data dout=ramladdm;else /write data ramladdm=din;endendmodule 11/14/202227Microelectronics School Xidian University module ram_single_tb;reg clk,we_n,cs_n;reg 2:0addm;reg 7:0din;wire 7:0dout;ram_single U1(.clk(clk),.addm(addm),.cs_n(cs_n),.

36、we_n(we_n),.din(din),.dout(dout);initial begin clk=0;addm=0;cs_n=1;we_n=0;din=0;#5 cs_n=0;#315 we_n=1;end always#10 clk=clk;initial begin repeat(7)begin#40 addm=addm+1;din=din+1;end#40 repeat(7)#40 addm=addm-1;end endmodule例：用例：用Verilog HDL设计深度为设计深度为8，位宽为，位宽为8的双端口的双端口RAM。双口双口RAM具有两套地址总线，一套用于读数据，另一套用

37、于写数据。具有两套地址总线，一套用于读数据，另一套用于写数据。二者二者可以分别独立操作。可以分别独立操作。11/14/202228Microelectronics School Xidian University module ram_dual(q,addr_in,addr_out,d,we,rd,clk1,clk2);output 7:0 q;/output data input 7:0 d;/input data input 2:0 addr_in;/write data address signal input 2:0 addr_out;/output data address sign

38、al input we;/write data control signal input rd;/read data control signal input clk1;/write data clock input clk2;/read data clock reg 7:0 q;reg 7:0 mem7:0;/8*8 bites register always(posedge clk1)begin if(we)memaddr_in=d;end always(posedge clk2)begin if(rd)q=memaddr_out;endendmodule11/14/202229Micro

39、electronics School Xidian University module ram_dual_tb;reg clk1,clk2,we,rd;reg 2:0addr_in;reg 2:0addr_out;reg 7:0d;wire 7:0q;ram_dual U1(.q(q),.addr_in(addr_in),.addr_out(addr_out),.d(d),.we(we),.rd(rd),.clk1(clk1),.clk2(clk2);initial begin clk1=0;clk2=0;we=1;rd=0;addr_in=0;addr_out=0;d=0;#320 we=0

40、;rd=1;end always begin#10 clk1=clk1;clk2=clk2;end initial begin repeat(7)begin#40 addr_in=addr_in+1;d=d+1;end#40 repeat(7)#40 addr_out=addr_out+1;end endmodule（2）ROM的Verilog HDL描述ROM即只读存储器，是一种只能读出事先存储的数据的存储器，其特性是存入数据无法改变，也就是说这种存储器只能读不能写。由于ROM在断电之后数据不会丢失，所以通常用在不需经常变更资料的电子或电脑系统中，资料并不会因为电源关闭而消失。11/14/2

41、02230Microelectronics School Xidian University module rom(dout,clk,addm,cs_n);input clk,cs_n;input 2:0 addm;output 7:0 dout;reg 7:0 dout;reg 7:0 rom7:0;initial begin rom0=8b0000_0000;rom1=8b0000_0001;rom2=8b0000_0010;rom3=8b0000_0011;rom4=8b0000_0100;rom5=8b0000_0101;11/14/202231Microelectronics Sch

42、ool Xidian University rom6=8b0000_0110;rom7=8b0000_0111;endalways(posedge clk)begin if(cs_n)dout=8bzzzz_zzzz;elsedout=romaddm;end endmodulemodule rom_tb;reg clk,cs_n;reg 2:0addm;wire 7:0dout;rom U1(.dout(dout),.clk(clk),.addm(addm),.cs_n(cs_n);initial begin clk=0;addm=0;cs_n=0;end always#10 clk=clk;

43、initial begin repeat(7)#20 addm=addm+1;endendmodule6.2.6 FIFO设计设计FIFO（First In First Out）是一种先进先出的数据缓存器，通常用于接口电路的数据缓存。与普通存储器的区别是没有外部读写地址线，可以使用两个时钟分别进行写和读操作。FIFO只能顺序写入数据和顺序读出数据，其数据地址由内部读写指针自动加1完成，不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址。FIFO由存储器块和对数据进出FIFO的通道进行管理的控制器构成，每次只对一个寄存器提供存取操作，而不是对整个寄存器阵列进行。FIFO有两个地址指针，

44、一个用于将数据写入下一个可用的存储单元，一个用于读取下一个未读存储单元的操作。读写数据必须一次进行。11/14/202232Microelectronics School Xidian University 其读写过程如下图所示：11/14/202233Microelectronics School Xidian University 当一个堆栈为空时（图A），读数据指针和写数据指针都指向第一个存储单元，如所示；当写入一个数据时（图 B）写数据指针将指向下个存储单元；经过七次写数据操作后（图 C）写指针将指向最后一个数据单元；当经过连续八次写操作之后写指针将回到首单元并且显示堆栈状态为满（图

45、D）。数据的读操作和写操作相似，当读出一个数据时，读数据指针将移向下一个存储单元，直到读出全部的数据，此时读指针回到首单元，堆栈状态显示为空。一个FIFO的组成一般包括两个部分：地址控制部分和存储数据的RAM部分。如下图所示。地址控制部分可以根据读写指令生成RAM地址。RAM用于存储堆栈数据，并根据控制部分生成的地址信号进行数据的存储和读取操作。这里的RAM采用的是前面提到的双口RAM。11/14/202234Microelectronics School Xidian University 11/14/202235Microelectronics School Xidian Universi

46、ty 例：用Verilog HDL设计深度为8，位宽为8的FIFO/顶层模块：module FIFO_buffer(clk,rst,write_to_stack,read_from_stack,Data_in,Data_out);input clk,rst;input write_to_stack,read_from_stack;input 7:0 Data_in;output 7:0 Data_out;wire 7:0Data_out;wire stack_full,stack_empty;wire 2:0 addr_in,addr_out;FIFO_control U1(.stack_fu

47、ll(stack_full),.stack_empty(stack_empty),.write_to_stack(write_to_stack),.write_ptr(addr_in),.read_ptr(addr_out),.read_from_stack(read_from_stack),.clk(clk),.rst(rst);ram_dual U2(.q(Data_out),.addr_in(addr_in),.addr_out(addr_out),.d(Data_in),.we(write_to_stack),.rd(read_from_stack),.clk1(clk),.clk2(

48、clk);endmodule11/14/202236Microelectronics School Xidian University/控制模块：module FIFO_control(write_ptr,read_ptr,stack_full,stack_empty,write_to_stack,read_from_stack,clk,rst);parameter stack_width=8;parameter stack_height=8;parameter stack_ptr_width=3;output stack_full;/stack full flagoutput stack_e

49、mpty;/stack empty flagoutput stack_ptr_width-1:0 read_ptr;/read data addressoutput stack_ptr_width-1:0 write_ptr;/write data address input write_to_stack;/write data to stackinput read_from_stack;/read data from stackinput clk;input rst;reg stack_ptr_width-1:0 read_ptr;reg stack_ptr_width-1:0 write_

50、ptr;reg stack_ptr_width:0 ptr_gap;reg stack_width-1:0 Data_out;reg stack_width-1:0 stackstack_height-1:0;11/14/202237Microelectronics School Xidian University/stack status signalassign stack_full=(ptr_gap=stack_height);assign stack_empty=(ptr_gap=0);always(posedge clk or posedge rst)beginif(rst)begi