数字电路7..1.ppt

1、1 1逻辑电路分为两大类：逻辑电路分为两大类：combinational logic circuit（组合逻辑电路）（组合逻辑电路）sequential logic circuit（时序逻辑电路）（时序逻辑电路）任何时刻的输出仅取决于当时的输入。任何时刻的输出仅取决于当时的输入。任一时刻的输出不仅取决于当时的输入，任一时刻的输出不仅取决于当时的输入，还取决于过去的输入序列。还取决于过去的输入序列。电路特点：无反馈回路、无记忆元件电路特点：无反馈回路、无记忆元件电路特点：有反馈回路、有记忆元件电路特点：有反馈回路、有记忆元件2 2 Latches and Flip-flops Clocked S

2、ynchronous State-Machine Analysis Clocked Synchronous State-Machine DesignChapter 7 Chapter 7 Sequential Logic Sequential Logic Design PrinciplesDesign Principles（时序逻辑设计原理）（时序逻辑设计原理）3 37.1 7.1 BistableBistable Elements Elements（双稳态元件）（双稳态元件）QQ_LIt has two stable states：Q=1 and Q=0 bistable circuit（双

3、稳电路）双稳电路）When power is first applied to the circuit,it randomly comes up in one state or the other and stays there forever.4 4Vin1Vout1Vin2Vout2Vout2Vin2=Vin2=Vout2stable 稳态metastable 亚稳态QQ_LVin1 Vout1Vin2 Vout2Analog AnalysisAnalog Analysis（模拟分析）（模拟分析）5 5亚稳态的存在使电路的状态可能出亚稳态的存在使电路的状态可能出现不确定性。现不确定性。稳态

4、稳态稳态稳态亚稳态亚稳态 Random noise will tend to drive a circuit that is operating at the metastable point toward one of the stable operating points.从一个从一个“稳态稳态”转换到另一个转换到另一个“稳稳态态”需加一定宽度的脉冲（足够的驱需加一定宽度的脉冲（足够的驱动）。动）。Metastable BehaviorMetastable Behavior（亚稳态特性）（亚稳态特性）Vin1Vout1=Vin2=Vout26 67.2 7.2 Latches and Fl

5、ip-FlopsLatches and Flip-Flops（锁存器与触发器）（锁存器与触发器）LatchLatch change its outputs according to its inputs directly at any time.Flip-FlopFlip-Flop change its outputs only when a clocking signal is changing(at the edge of a CLK signal).S-R Latch D Latch D Flip-Flop J-K Flip-Flop T Flip-FlopContents:basic

6、building blocks of most sequential circuits7 7QQNRS（1）S=R=0The circuit retains previous state.00QQLNOR gate not gate Q*=Q QN*=QNNext state（新态）（新态）Present state（原态）（原态）S-R LatchS-R LatchPrinciples:8 8QQNRS10（2）S=0,R=1a.原态：Q=0，QN=101新态：Q*=0，QN*=1b.原态：Q=1，QN=0新态：Q*=0，QN*=1锁存器锁存器清清0：Q*=0 QN*=1即使即使S,R无效无

7、效(=0),锁存器仍能锁定锁存器仍能锁定0态态.Reset10(a)QQNRS1001(b)0101S-R LatchS-R LatchPrinciples:9 9QQNRS01（3）S=1,R=0a.原态：原态：Q=1，QN=010新态：新态：Q*=1，QN*=0b.原态：原态：Q=0，QN=1新态：新态：Q*=1，QN*=0锁存器锁存器置置1：Q*=1 QN*=0即使即使S,R无效无效(=0),锁存器仍能锁定锁存器仍能锁定1态态.Set01(a)QQNRS0110(b)0110S-R LatchS-R LatchPrinciples:1010QQNRS（4）S=R=100Q*=QN*=0当

8、当S,R无效无效(=0)时，时，11QQN00状态不确定！“禁止禁止”S-R LatchS-R LatchPrinciples:1 0 1 0 11 11S-R LatchS-R LatchS QR QNLogic symbolResetSet清清0置10 00 11 01 1S Rlast state0 11 00 0Q QNFunction tableS QR QQQNRS0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1S R01001100QQ*状态转移真值表1212 tpw(min)0 00 11 01 1S Rlast state0 11 00 0Q

9、QNSRQ tpLH(SQ)tpLH(RQ)SRQQNpropagation delay禁止输入禁止输入 Typical operationminimum-pulse-width1313S S -R LatchR LatchS_L=R_L=11 11 00 10 0S_L R_Llast state0 11 01 1Q QNFunction tableretain previous stateS_L=1,R_L=0Q=0,QN=1S_L=0,R_L=1Q=1,QN=0S_L=R_L=0Q=QN=1，不定状态SR 清清 0 0 置置 1 1禁止状态禁止状态S QR QLogic symbolQQ

10、NS_LR_L1414S-R Latch with EnableS-R Latch with EnableSRC0 X X1 0 01 0 11 1 01 1 1C S Rlast statelast state0 11 01 1Q QN Function table(1)C=0,retain previous state(2)C=1,like an S-R latch注意：当S=R=1时，若C由10，则下一状态不可预测。QQNS_LR_L 清清 0 0 置置 1 1禁止状态禁止状态SCRQQLogic symbol1515QSRC Typical operationS-R Latch wit

11、h EnableS-R Latch with Enable1616D LatchD LatchD=1时，时，Q=1C=0，QQNSRDC输出状态保持不变；输出状态保持不变；输出随输入状态而改变。输出随输入状态而改变。C=1，D=0时，时，Q=0Q=Dtransparent latch透明锁存器透明锁存器D QC QLogic symbolC D Q QN1 0 0 11 1 1 0 0 X Function tablelast state1717QDC tpLH(CQ)tpHL(DQ)tpLH(DQ)tpHL(CQ)tsetupsetup time建立时间tholdhold time保持时间

12、There is a window of time around the falling edge of C when the D input must not change.propagation delay:tpLH(CQ),tpHL(CQ),tpHL(DQ),tpLH(DQ)D LatchD Latch Typical operation1818Application of LatchApplication of LatchD QC QD QC QD QC QD QC QDIN3:0 WRDOUT3:0RDmemory1919只用一片只用一片1 1位全加器实现？位全加器实现？X YCI

13、COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串串行行加加法法器器C1C2C1S0X0 Y0C0X YCI COSC2S1X1 Y1C1反馈反馈C3S2X2 Y2C2利用利用反馈反馈和时钟控制和时钟控制Application of LatchApplication of Latch Iterative Circuit2020X YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串串行行加加法法器器C1C2暂存暂存X YCI COSCi+1SiXi YiCi时钟控制时钟控制利用锁存器暂存运算结果。利用锁存器暂

14、存运算结果。Application of LatchApplication of Latch Iterative Circuit2121暂存暂存X YCI COSCi+1SiXi YiCi时钟控制时钟控制利用锁存器暂存运算结果。利用锁存器暂存运算结果。Q DQ CXYCISiCi+1XiYiCiSCOCLK串行输入、串行输出需要有效的时钟控制Application of LatchApplication of Latch Iterative Circuit2222D Flip-flopD Flip-flopD QC QD QC QQQNDCLK(1)CLK=0时，时，(2)CLK=1时，时，主

15、锁存器工作，接收输入信号主锁存器工作，接收输入信号 Qm=D;从锁存器不工作，输出从锁存器不工作，输出 Q 保持不变保持不变.主锁存器不工作，主锁存器不工作，Qm 保持不变保持不变;从锁存器工作，将从锁存器工作，将 Qm 传送到输出端传送到输出端.主主 master从从 slaveQm2323DCLKQQmD QC QD QC QQQNDCLK主主 master从从 slaveQmD Flip-flopD Flip-flop2424DCLKQD CLK Q QN0 0 11 1 0X 0 保 持X 1 保 持function tableD Q CLK Qlogic symboledge-tri

16、ggered behaviorPositive-edge-triggered D flip-flop(正边沿触发式正边沿触发式D触发器触发器)sample the D input only at the rising edge of a CLK signal.characteristic equationQ*=D“*”表示时钟触发沿到表示时钟触发沿到来后输出来后输出Q的新状态。的新状态。2525DCLKQDC QD触发器触发器 边沿有效边沿有效D锁存器锁存器 电平有效电平有效2626tpLH(CQ)tpHL(CQ)CLKQtsetupSetup time thold Hold timel Timing Behavior propagation delay (CLKQ)It has a setup and hold time window during which the D inputs must not change.2727（第三版）（第三版）（第四版）（第四版）第一次作业7.27.37.277.47.57.41