HP3070TrainingMaterial安捷伦在线测试--入门指导书.pptx

1、安捷伦在线测试-入门指导书Agilent ICT Tester(Outline)（SOF一TWAR）E一一、如如何何开开关关测测试试机机器器1、开机假设HP3070正处于关机状态，先把机器后面的红色旋扭开关旋转到一的位置，然后把绿色按钮开关打到ON的位置，此时机器已经处于上电状态。这时候就可以打开主机电源，此时显示屏的内容会有一定的变化，这时不要动键盘和鼠标直到显示要你输入用户名为止。输入用户名user1后，再输入密码celetest8（注意保密），此时已经登入到HP-UX 系统中，打开一个BT-BASIC窗口，输入命令testhead power on，等几分钟出现下图后就表示testhea

2、d已经上电了，机器可以测试线路板了。2、关机（SHUTDOWN）假设HP3070处于开机状态，松开夹具（如果测试头上放有测试夹具），在BT-BASIC窗口输入testhead power off，再关闭所有窗口。然后点击exit图标，在出现的输入用户名窗口中输入shutdown，此用户无密码，可直接在输入密码 窗口中按enter键，此时也不要去碰鼠标和键盘，直到有提示可以关闭电源后再关闭主机电源，然后是绿色按钮开关 和红色旋钮开关。机器这时已正常关机。SHUTDOWN输入用户名提示窗口（开机）输入用户名提示窗口（关机）输入密码提示窗口（celetest8)为了安全起见,密码将不会显示出来.*H

3、P3070系统用户窗口界面文件管理器类似于windows操作系统中的“我的电脑”工具菜单系统说明书菜单垃圾箱按此退出登陆开始测试按钮首先确认要测试的是那种线路板，然后选择相应的夹具放到测试头上吸合夹具。点击鼠标右键弹出右图所示菜单，拖动鼠标选择New BT-BASIC Window 命令，此时会弹出 BT-BASIC窗口，用msi命令进入相应的程序目录后，输入命令gettestplan或输入loadtestplan，引号要同时为单引号或同时为双引号.此时点击按sstt钮aarrSttTART或在BT-BASIC窗口中输入命令run后就可以开始测试 线路板了。停止测试按钮二二、如如何何开开始始线

4、线路路板板的的测测试试BT-BASIC 窗口命令行(command line)编辑区(edit area)功能键 softkey进程号 ID模式model测试头已上电标志测试界面常常用用的的BT-BASIC命令命令cat列出当前目录的内容,类似于DOS的dir命令change用新的字符串代替已存在的字符，不区分大小写changem同上，作用域在高亮显示区，而不是整个编辑区copy to拷贝文件，此文件名不存在copy over拷贝文件，文件名存在就覆盖，否则建立新的文件create dir建立一个新的目录delete删除高亮显示区duplicate复制高亮显示区到命令编辑区edit把光标放到指

5、定行的位置fetch拷贝指定编辑区的一行到命令编辑区find查找指定的字符串unlink删除文件findn查找指定字符串，并继续查找下一个get清除编辑区内容并打开文件显示在编辑区list把编辑区内容全部显示到输出设备上load同getmerge合并一个或多个文件到另一个文件中move移动高亮显示区到当前光标处msi改变路径msi$显示当前目录number显示当前光标所在行列scratch清除编辑区save存盘为另一个文件re-save存盘常常用用的的BT-BASIC命命令令(续续表表)board graphics打开板子的组装图常常用用的的BT-BASIC命命令令(续续表表load boar

6、d把一些目标文件调入内存，如board.o,wirelist.odebug board打开Pushbotton debug 窗口，进行程序调试board consultant打开board cons图，进行如元件外形描述的编辑fixture consultant打开fix consultant图，可以查找夹具上的测试针debug end结束Pushbotton debug 进程board graphics end 结束board grap 进程compile编译文件，使之生成目标文件testhead power on给测试头上电（开机时用）testhead power off 给测试头下电（关

7、机时用）testhead is 1使测试头处于受控制使用状态testhead is*关闭测试头的使用)faon/faoff打开/关闭真空气阀开关fixture lock吸合夹具fixture unlock 松开夹具unpowered初始化系统，为不上电测试作准备powered初始化系统，为上电测试作准备execute在BT-BASIC 窗口中执行SHELL命令exit退出BT-BASIC 窗口clear nrun使nrun的计数为零find pins激活测针查找功能，用guided probe查找测针常常用用的的BT-BASIC命命令令(续续表表)Pushbutton debug 窗口fix

8、consultant（针点图）PCB board graphicsBoard consultant四四、常常用用的的shell命命令令介介绍绍man man显示man命令的说明kill ID强行终止某一进程cd dir改变目录路径mv file1 file2文件移动或重命名pwd显示当前路径名ftp文件传输ll dir/file 显示当前路径内容的长列表passwd改变密码ls dir/file 显示当前路径内容的短列表clear清屏cp file1 file2文件复制，加-R复制目录tar文件压缩rm file删除文件，加-R删除目录exit退出进程mkdir建立目录more查看文件内容rm

9、dir删除目录diff比较两文件的差异du查看磁盘容量vi打开vi编辑器dir-catalog|file1-source file|file2-o特别注意特别注意!慎用此命令,除非你知道自己在做什么!rm-r*SHELL窗口五五、testplan 的的简简介介及及测测试试原原理理call Pre_shortscall Shorts.call Analog_testscall testjetcall digitalsub Characterize learn capacitance on learn capacitance off subendsub Pre_Shorts subend sub

10、Shortstest“shorts”subendsub Analog_Tests test“analog/c4”test“analog/r56”subendsub Digital_Tests test“digital/u1”test“digital/u2”subend主程序子程序短短路路定定义义:短短路路,就就是是两两个个测测试试点点之之间间的的阻阻抗抗小小于于或或等等于于预预设设的的门门限限值值.开开路路定定义义:开开路路,就就是是两两个个测测试试点点之之间间的的阻阻抗抗大大于于预预设设的的门门限限值值.A Shorts Test is testing for unexpected shor

11、ts on the board;it requires the impedance between nodes to be greater than the threshold(open)to give a PASS indication.An Opens Test is testing for unexpected opens on the board;it requires impedance between nodes to be less than or equal to the threshold(short)to give a PASS indication.1.短路测试原理(Un

12、power)Example:Shorts Test fileOpen testShorts testOpen testBCDshort“A”to“D”sourceAdetectorSDShorts test侦测:测试针首先选择“shorts”file里的第一个测试点(假设是A点),将它与信号源相连,再将列表中的其它点短接后与A测试,看是否短路.如没有短路,则第二个测试点(假设B点),重复A的测试过程.隔离(排除法):如果发现短路,依次断开那些预先短接的测试点,重复上述“侦测”各步骤,直至发现短路点.Isolate a short1.检测A与BCDE之间有无短路.2.在检测B与CDE是否短路时,

13、发现短路.3.首先隔离C点,DE短接,仍发现短路.说明B与 DE间有短路.再隔离D点,B与E之间短路.最后隔离E点,发现没有短路,说明BD之间没有短路.4.最终发现B与E短路.图解:如何发现B与E之间短路Phantom shortsPhantom short:detection find short but isolation cant find典型模拟元件测试方法2.摸拟元件测试原理(Unpower)disconnect all connect s to“N1”Resistor typical test program:connect i to“N2”connect g to“N100”re

14、sistor 10k,5.5,5,re5,ar0.1三线测试(S bus、I bus、G bus)1.Sbus2.Ibus3.Gbus4.Abus5.Bbus6.Lbus六线测试（S bus、A bus、I bus、B bus、G bus、L bus）Capacitor Test!201 10029453270000!IPG:rev B.03.42 Sat Oct 13 11:55:28 2001!C o m m o n Lead Resistance 100m,C o m m o n Lead Inductance 1.00u!Fixture:EXPRESSon failurereport

15、parallel devices report r1 15.0kend on failureC=1/2f ZcCapacitor test:Zc=1/2fc!-表示注解disconnect all!断开所有继电器断开所有继电器connect s to“GND”;a to“GND”!连接连接 S bus 和和 A bus 到到 GND 点点 connect i to TREE1022!连接连接 I bus 到到TREE 1022 点点 connect g to+5!连接连接 G bus 到到+5 点点capacitor 100n,13.4,8.66,fr1024,re3,wb,ar100m,sa

16、,en,n o co mp上限、下限、频率、反馈电阻、测试选项，具体含义见前面表格Diode&Zener Test!201 8852321590000!IPG:rev B.02.54 M o n Jan 19 09:49:20 1998!C o m m o n Lead Resistance 500m,C o m m o n Lead Inductance 1.00u!Fixture:EXPRESS disconnect all connect s to VCC connect i to$34diode 728m,413m,idc5.0m,co3.0,ar828m!201 9242176620

17、000!IPG:rev B.03.13 W e d Mar 31 11:25:15 1999!C o m m o n Lead Resistance 500m,C o m m o n Lead Inductance 1.00u!Fixture:EXPRESS on failurereport parallel devices report q23 q23:fet 100,20.0end on failuredisconnect all connect s to TREE89 connect i to B0 connect g to VFnfet 81.6,10.0,re1,ar50.0mFET

18、 Test Configurationa m amp模li拟tud测e 试信 号选电项压参幅 度数，介直绍流-10.00V-+10.00V,交流0.00ar ASRU range ARSU增益范围，0-+10Vidc DC current DC信号电流大小，100ua-150ma comp capacitor compensation 需要电容补偿 nocomp no compensation不需要电容补偿fr frequency交流信号频率，128Hz、1024Hz、8192Hzre reference element 反馈电阻，re1-re6表示反馈电阻分别为 wa wait 在产生激励和

19、获得读数之间等待，0-9.9999Ssa use the A bus to sense the S bus 利用A bus在S bus处检测信号电 sb use the B bus to sense the I bus 利用B bus在I bus处检测电流计 sl use the L bus to sense the G bus 利用L bus在G bus处检测隔离点 en enhancement 增强测试，其测试原理见下图ed extra digit 克服线周期求测量的积分，可以屏蔽线频率50Hz/6增增强强测测试试原原理理Enhancement(en)模拟测试选项参数介绍co voltag

20、e compliance限制电源电压，0-10Vico current compliance 限制MOA输入电流大小，0=35ma，1=150maof offset使交流信号产生一个直流偏置电压，-10V-+10VDCfi filter 取平均值，1-9999op opposite 对测试结果取反dwa detector wait 在使用en选项时，使detector在测量之前等待指定时间，0-1swb wideband 选用MOA宽频特性，原理见下图pf pass/fail 用数字1(pass)和0(fail)取代测试值pm parallel mode为电容和电感选择并联测试模式，电容测试常

21、用pmsm serial mode为电容和电感选择连续测试模式，电感测试常用smad adjust 允许在测量前调试可变元件，如可调电阻，可带参数0、1、2pc parallel capacitor 并联一个100pf的电容到被测元件上，仅在调试时使用详细注解请见附页Wideband theoryWideband(wb)Versus Narrowband Frequency Responses3.Testjet test(Unpower)HP TestJet ArchitectureH P TestJet is an unpowered test of the connectivity fro

22、m each pin on a device to the circuit board.The system uses the H P TestJet hardware to measure the capacitance from a pin of a device to the H P TestJet probe.The measurement is repeated for each pin on the device,except power and ground pins.Pins that are tied together are tested as one pin.Remark

23、:The S(source)bus to the pin being tested,the I(input)bus to the HP TestJet probe,and the G(guard)bus to all other pins on the device.The testjet FileThe testjet file is the test file for all devices to be tested with HP TestJet;this one test file includes the tests for all HP TestJet devices.defaul

24、t threshold low 200 high 10000 default throughput adjustment 1!throughput adjustment 0device u101”;threshold low100 high 10000test pins 1test pins 2,3test pins 4,5,6!test pins 7!Ground pins commented by H P IPG.test pins 8test pins 11;threshold low 20 high 10000 test pins 12test pins 13!test pins 14

25、!Fixed pins commented by H PThe defaIuPlGt.threshold statement sets the test thresholds for all the devices in the file.The defaiunlatctchersosuigbhlpeuptptiandsju9s,t1m0ent statement enables or disables throughput adjustmenetnfdordealvlictehe devices in the file.There is a device/end device block f

26、or each device to be tested.The device statementspecifies the device designator.If the device is mounted on the bottom side of the board,the device”statement includes the bottom keyword.The test pins statement specifies the pin or pins to be tested.Pins that are tied together inthe circuit are speci

27、fied and are tested together.The inaccessible pins statement declares pins that are not tested because they are not accessible.This statement always appears at the end of the device block.Testjet Probe AssembleTestjet Probe AssembleHP TestJet Probe and Mux Card Connections.Pin Numbers for the Right-

28、Angle Connector.Mux Card Jumpers J4 and J5.An Example of HP TestJet Wiring in the Top Side of the Fixture.4.The Setup_Power_Supplies Routinesub Setup_Power_Supplies global Pslimitcpssps 1,5.00,0.50;optimize|rps 1,V,I|print V,I sps 2,-5.00,2.00;optimizePslimit=pslimitpass deviceif Pslimit then dpsfai

29、l device I=1for Pscount=1 to 2if binand(Pslimit,I)then report “Power Supply Number”report Pscountreport “In Current Limit”end ifI=2*Inext Pscount report“”report“Check for backwards”report“ICs or Capacitors.”subenddps-Disconnect Power Supply report“-”end ifcps-Connect Power Supply sps-Set Power Suppl

30、yrps-Report Power Supply1,5.00,0.50第一组电源，上电+5V，允许最大电流0.50A第二组电源，上电-5V，允许最大电流2.00A2,-5.00,2.00如果不能上电，则执行此语句来循环判断哪组电源不能上电打印第一组电源的上电打印第一组电源的上电电压和允许最大电流电压和允许最大电流 有optimize选项 表示两组同时上电5.数字测试原理(Powered)在向量中的时间分隔段Timing in a vectorThe parts of a Digital Test（VCL简介)!Declaration Section!Device Type!assignment

31、 section!Timing SectionDetails are coveredin Advanced Digital Class!Vector Definition Section Vector Initial_Stateset Reset to“0”set CS_bar to“0”.!Vector Execution section unit“Test Reset”execute Initial_State execute Assert_reset.Vector Control Language1245910121336811NAND GATE与非门Truth Table 真值表Dig

32、ital library(Declaration Section)!7400!NAND,2-Input,Quad!revision A.01.00combinatorial vector cycle 500n receive delay 400nassignassignVCCG N Dto pins 14to pins 7assign E1_Inputs to pins 1,2assign E2_Inputs to pins 4,5assign E3_Inputs to pins 9,10assign E4_Inputs to pins 12,13assign E1_Output to pin

33、s 3assign E2_Output to pins 6assign E3_Output to pins 8assign E4_Output to pins 11power VCC,G N Dfamily TTLinputs E1_Inputs,E2_Inputs,E3_Inputs,E4_Inputs outputs E1_Output,E2_Output,E3_Output,E4_Output注解声明测试类型定义每一个向量的持续时间定义元件引脚组名称指定哪些引脚组被连接到电源点指定用于信号输入的元件引脚组定义逻辑电平指定用于信号输出的元件引脚组Digital library test(V

34、ector Definition Section)vector E1_Input_00to 00to 1set E1_Inputs set E1_Outputend vectorvector E1_Input_01to 01to 1set E1_Inputs set E1_Outputend vectorvector E1_Input_10to 10to 1set E1_Inputs set E1_Outputend vectorvector E1_Input_11to 11to 0set E1_Inputs set E1_Outputend vectorvector E4_Input_00s

35、et E4_Inputs to 00 set E4_Output to 1end vectorvector E4_Input_01set E4_Inputs to 01 set E4_Output to 1end vectorvector E4_Input_10set E4_Inputs to 10 set E4_Output to 1end vectorvector E4_Input_11set E4_Inputs to 11 set E4_Output to 0end vector向量单元指 定高 低电平向量开始结束标志Digital library(unit section)unit E

36、lement number 1 execute E1_Input_11 execute E1_Input_01 execute E1_Input_00 execute E1_Input_10end unitunit Element number 2 execute E2_Input_11 execute E2_Input_01 execute E2_Input_00 execute E2_Input_10end unitunit Element number 3 execute E3_Input_11 execute E3_Input_01 execute E3_Input_00 execut

37、e E3_Input_10end unitunit Element number 4 execute E4_Input_11 execute E4_Input_01 execute E4_Input_00 execute E4_Input_10end unit测试单元执行向量各种逻辑符号的含义“0”set a logic low on the node.“1”set a logic high on the node.“K”keep the previous state.“T”toggle from the previous state.“Z”set the device to a high i

38、mpedance state.“X”dont care this receiver.Overdrive and BackdriveVCCVector E1_Input_11set A to“1”set B to“1”set C to“0”end vectorABCVCCBack drive currentstandard_cmos safeguard filePATH:/hp3070/standard/safeguard/standard_cmos!801 5916888000000parameters standard_cmos!subfamily:standard C M O S!char

39、acteristics:low level output current =3 m A!Vcc=5 V!backdrive current of 0.005 for 0,0.050 for 1 overdrive power 0.02,0.02 dissipated by heat source heat source 100 by 10,1 per outputoperating temperature 40thermal resistance 60 package ceramicend parametersLibrary level Safeguard File!Standard Safe

40、guard Templateinclude standard_cmosuse parameters standard_cmos for TL7702AH_1 use parameters standard_cmos for 28SCID0490CH_1 use parameters standard_cmos for 74ABT244H_3 use parameters standard_cmos for 74F08H_1use parameters standard_cmos for S02F use parameters standard_cmos for 358H_2use parame

41、ters standard_cmos for 74F112H_2 use parameters standard_cmos for 74F175H_1 use parameters standard_cmos for 74F74H_2 use parameters standard_cmos for 74F163H_1 use parameters standard_cmos for 74F32H_1 use parameters standard_cmos for 10H125P_3 use parameters standard_cmos for 74F38H_1Board level S

42、afeguard Fileparameters standard_cmosbackdrive current of 5 m for 0,5 0 m for 1 bond wire 2540 by 25.4heat source 100 by 10,1 per outputoperating temperature 40overdrive power 20m,2 0 m dissipated by heat source package ceramicthermal resistance 60 end parametersuse parameters standard_cmos for u1 u

43、se parameters standard_cmos for u2 use parameters standard_cmos for u3 use parameters standard_cmos for u4 use parameters standard_cmos for u5 use parameters standard_cmos for u6 use parameters standard_cmos for u8 use parameters standard_cmos for u9 use parameters standard_cmos for u10 use paramete

44、rs standard_cmos for u11 use parameters standard_cmos for u12Digital compiler safeguard checkDigital/u15C O M P I L A T I O N S U M M A R Y31 vectors executed19 vector R a m slots used,0%full 32 sequence ram slots used,0%full 13 directory ram slots used,0%fullS A F E G U A R D S U M M A R Ysafeguard

45、 status:Not Inhibited Estimated test time:3.60e-05Safe Test time(device):5.99e-01(u16)201 lines,0 errers,0 warnings,object producedDisable issuecsUUT2 U2UpsteamUUT1deviceU1U21outputInputDisable description in library!Q M V 2 8 8U21 Library!setup only!revision A.01.00vector cycle 500n receive delay 4

46、00nassign assignVCC to pins 1,2,3,4,5G N D to pins 25,26,27,29,30assign assign assignIO to pins 5,6,7,8,9,10,11,12,13,14,15,16 IO to pins 17,18,19,20,21,22,23,24CS to pins 28family TTL power VCC,GNDinputs CS bidirectional IOdisable IO with CS to 0Disable in execute test!U2 executable testassign Disa

47、blegroup to nodes TREE 1343”default 0 inputs Disablegroupassign DisableFamilyTTL to nodes TREE 1343 family TTL on DisableFamilyTTLinputs DisableFamilyTTL!IPG:Safeguard will ignore disabled outputs disabled device u21 pins 5,6,7,8,9,10,11,12 disabled device u21 pins 13,14,15,16,17,18,19 disabled devi

48、ce u21 pins 20,21,22,23,24!IPG:with pin 28 on node TREE 1343The node TREE 1343(U21 Pin CS)keep at low level during U2 Test6.Analog Functional test(Powered)ARSU Resources:Sourcea:auxiliary sourcei:detector high l:detector lowrcva,rcvb,rcvc:frequency detectoResource specificationSourcerangeunitDCV-10-

49、+10VdcSINE0-7.0VrmsSQUARE0-10VpkTRIANGLE0-10VpkAuxiliary source:-10-+10VdcFrequency detector:1-60MHz!IPG:rev B.03.42 Sat Oct 13 11:56:05 2001!Quad TTL-ECL Translatortest powered analogpower pins 8,9,16nonanalog pins 6 connect l to ground test TRANSLATOR1_4 test TRANSLATOR1_2end test!subtest TRANSLAT

50、OR1_4 connect s to pins 5 connect i to pins 4source dcv,amplitude 2.5,icompliance 1,on detector dcv,expect-2measure-1.6,-2wait 50msource dcv,amplitude 0.3,icompliance 1,on detector dcv,expect-1measure-0.7,-1end subtestsubtest TRANSLATOR1_2.end subtestAnalog Function Test FileAnalog function测试标志Pins