1、Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Chapter 13:Introduction to Switched-Capacitor Circuits13.1 General Considerations13.2 Sampling Switches13.3 Switched-Capacitor Amplifiers13.4 Switched-C
2、apacitor Integrator13.5 Switched-Capacitor Common-Mode Feedback Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.2General Considerations For continuous-time amplifier Fig.(a),Vout/Vin=-R2/R1 ideally Di
3、fficult to implement in CMOS technology Typically,open-loop output resistance of CMOS op-amps is maximized to maximize Av R2 heavily drops open-loop gain,affecting precision Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of
4、McGraw-Hill Education.3General Considerations In equivalent circuit of Fig.(b),we can write Hence,Closed-loop gain is inaccurate compared to when Rout=0 Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education
5、.General Considerations4 To reduce open-loop gain,resistors can be replaced by capacitors Fig.(a)Gain of this circuit is ideally C1/C2 To set bias voltage at node X,large feedback resistor can be added Fig.(b)Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution wi
6、thout the prior written consent of McGraw-Hill Education.General Considerations5 Feedback resistor is not suited to amplify wideband signals Charge on C2 is lost through RF resulting in“tail”Circuit exhibits high-pass transfer function given by Ddd only if Copyright 2017 McGraw-Hill Education.All ri
7、ghts reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.General Considerations6 RF can be replaced by a switch S2 is turned on to place op amp in unity gain feedback to force VX equal to VB,a suitable common-mode value When S2 turns off,node X retains
8、 the voltage allowing amplification When S2 is on,circuit does not amplify Vin Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.General Considerations7 In above circuit,S1 and S3 connect left plate of
9、C1 to Vin and ground,S2 for unity-gain feedback Assume large open-loop gain of op amp First phase:S1 and S2 on,S3 off Fig.(a)Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.General Considerations8 Her
10、e,and C1 samples the input Vin Second phase:At t=t0,S1 and S2 turn off and S3 turns on,pulling node A to ground Fig.(b)VA changes from Vin to 0,therefore Vout must change from zero to Vin0C1/C2 Fig.(c)Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without th
11、e prior written consent of McGraw-Hill Education.General Considerations9 Circuit devotes some time to sample input,setting output to zero and providing no amplification After sampling,for t t0,circuit ignores input voltage,amplifies sampled voltage Copyright 2017 McGraw-Hill Education.All rights res
12、erved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.General Considerations10 Switched-capacitor amplifiers operate in two phases:Sampling and Amplification Clock needed in addition to analog input Vin Copyright 2017 McGraw-Hill Education.All rights reserv
13、ed.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches11 Sampling circuit consists of a switch and a capacitor Fig.(a)MOS transistor can function as switch Fig.(b)since it can be on while carrying zero current Copyright 2017 McGraw-Hill Educ
14、ation.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches12 CK goes high at t=t0 Assume Vin=0 and capacitor has initial voltage VDD At t=t0,M1 is in saturation and draws current As Vout falls,at some point M1 goes into tr
15、iode region CH is discharged until Vout reaches zero For Vout 2(VDD-VTH),transistor is an equivalent resistor Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches13 If Vin=+1 V,Vout(t=t
16、0)=+0 V and VDD=+3 V Terminal of M1 connected to CH acts as source,and the transistor turns on with VGS=+3 V but VDS=+1 V M1 operates in triode region and charges CH until Vout approaches+1 V For Vout +1 V,M1 exhibits an on-resistance of Copyright 2017 McGraw-Hill Education.All rights reserved.No re
17、production or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches14 When switch is on Fig.(a),Vout follows Vin When switch is off Fig.(b),Vout remains constant Circuit“tracks”signal when CK is high and“freezes”instantaneous value of Vin across CH when CK goes
18、low Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches15 Suppose Vin=V0 instead of+1 V M1 is saturated and we have:Solving,As t ,Vout VDD-VTH so NMOS cannot pull up to VDD Copyright 2
19、017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches16 Similarly,PMOS transistor fails to operate as a switch if gate is grounded and drain senses an input voltage of|VTHP|or less On resistance ri
20、ses rapidly as input and output levels fall to|VTHP|above ground Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Speed Considerations17 Measure of speed is the time required for ou
21、tput to go from zero to the maximum input level after switch turns on Consider output settled within a certain“error band”V around final value If output settles to 0.1%accuracy after tS seconds,then V/Vin0=0.1%After t=tS,consider source and drain voltages to be approximately equal Copyright 2017 McG
22、raw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Speed Considerations18 Sampling speed is given by two factors:switch on-resistance and sampling capacitance For higher speed,large aspect ratio and sm
23、all capacitance are needed On-resistance also depends on input level for both NMOS and PMOS Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Speed Considerations19 To allow greater
24、input swings,we can use“complementary”switches,requiring complementary clocks Fig.(a)Equivalent on-resistance shows following behavior Fig.(b),revealing much less variation Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of M
25、cGraw-Hill Education.MOSFETS as Switches:Speed Considerations20 For high speed signals,NMOS and PMOS switches must turn off simultaneously to avoid ambiguity in sampled value If NMOS turns off t seconds before PMOS,output tends to track input for the remaining t seconds,causing distortion For modera
26、te precision,circuit below is used to provide complementary clocks Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Precision Considerations21 Speed trades with precision Channel Ch
27、arge Injection:For MOSFET to be on,a channel must exist at the oxide-silicon interface Assuming Vin Vout,total charge in the inversion layer is When switch turns off,Qch exits through the source and drain terminals(“channel charge injection”)Copyright 2017 McGraw-Hill Education.All rights reserved.N
28、o reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Precision Considerations22 Charge injected to the left is absorbed by input source,creating no error Charge injected to the right deposited on CH,introducing error in voltage stored on capac
29、itor For half of Qch injected onto CH,error(negative pedestal)equals Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Precision Considerations23 If all of the charge is deposited on
30、 CH,Since we assume Qch is a linear function of Vin,circuit exhibits only gain error and dc offset Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Precision Considerations24 Clock
31、Feedthrough:MOS switch couples clock transitions through CGD or CGS Sampled output voltage has error due to this give by Cov is the overlap capacitance per unit width Error V is independent of input level,manifests as constant offset in the input/output characteristic Copyright 2017 McGraw-Hill Educ
32、ation.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.MOSFETS as Switches:Precision Considerations25 kT/C Noise:Resistor charging a capacitor gives a total RMS noise voltage of On resistance of switch introduces thermal noise at output w
33、hich is stored on the capacitor when switch turns off RMS voltage of sampled noise is still approximately equal to Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Charge Injection Cancellation26 Charg
34、e injected by main transistor removed by a dummy transistor M2 M2 is driven by so that after M1 turns off and M2 turns on,channel charge deposited by M1 on CH is absorbed by M2 to create a channel If W2=0.5W1,then charge injected by M1,q1 is equal to that absorbed by M2 Copyright 2017 McGraw-Hill Ed
35、ucation.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.27Charge Injection Cancellation If W2=0.5W1 and L2=L1,effect of clock feedthrough is suppressed Total change in Vout is zero because Copyright 2017 McGraw-Hill Education.All rights
36、reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.28Charge Injection Cancellation Incorporate both PMOS and NMOS devices so that opposite charge packets injected cancel each other For q1 to cancel q2,we must have Cancellation occurs for only one inpu
37、t level Clock feedthrough is not completely suppressed since CGD of NFETs is not equal to that PFETs Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.29Charge Injection Cancellation Charge injection ap
38、pears as a common-mode disturbance,may be countered by differential operation q1=q2 only if Vin1=Vin2,thus overall error is not suppressed for differential signals Removes constant offset and nonlinear component Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution
39、 without the prior written consent of McGraw-Hill Education.30Unity-Gain Sampler/Buffer For discrete-time applications,unity-gain amplifier Fig.(a)requires a sampling circuit Fig.(b)Accuracy limited by input-dependent charge injected by S1 onto CH Copyright 2017 McGraw-Hill Education.All rights rese
40、rved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.31Unity-Gain Sampler/Buffer Consider the topology shown in Fig.(a)In sampling mode,S1 and S2 are on,S3 is off yielding circuit in Fig.(b)Thus,Vout=VX 0,and the voltage across CH tracks Vin At t=t0,when Vi
41、n=V0,S1 and S2 turn off and S3 turns on,yielding circuit of Fig.(c)amplification mode Op amp requires node X is still a virtual ground,Vout rises to approximately V0“frozen”for processing by subsequent stages Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution wi
42、thout the prior written consent of McGraw-Hill Education.32Unity-Gain Sampler/Buffer S2 turns off slightly before S1 during transition from sampling mode to amplification mode Charge injected by S2,q2 is input-independent and constant,producing only an offset After S2 turns off,total charge at node
43、X stays constant and charge injected by S1 does not affect output voltage Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.33Unity-Gain Sampler/Buffer Input-independent charge injected by S2 can be can
44、celled by differential operation as shown Charge injected by S2 and S2 appears as common-mode disturbance at nodes X and Y Charge injection mismatch between S2 and S2 resolved by adding another switch Seq that turns off slightly after S2 and S2,equalizing the charge at nodes X and Y Copyright 2017 M
45、cGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.34Unity-Gain Sampler/Buffer Precision Considerations:Assume op-amp has a finite input capacitance Cin and calculate output voltage when circuit goes from sampling to am
46、plification mode It can be shown from the above fig.that Circuit suffers from gain error of approximately Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.35Unity-Gain Sampler/Buffer Speed Consideratio
47、ns:In sampling mode,circuit appears as in Fig.(a)Use equivalent circuit of Fig.(b)to find time constant in sampling mode Total resistance in series with CH is Ron1 and the resistance between X and ground,RX Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution with
48、out the prior written consent of McGraw-Hill Education.36Unity-Gain Sampler/Buffer Since typically and ,Time constant in sampling mode is thus Consider circuit as it enters amplification mode Circuit must begin with Vout 0 and eventually produce Vout V0 For relatively small Cin,voltages across CL an
49、d CH do not change instantaneously so that VX=-V0 at the beginning of amplification Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.37Unity-Gain Sampler/Buffer Represent charge on CH by a voltage sour
50、ce VS that goes from zero to V0 at t=t0,while CH carries no charge itself The transfer function Vout(s)/Vin(s)can be obtained as This response is characterized by a time constant independent of op-amp output resistance Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distr
