1、Simple FSM design:Attendant call system Rising-edge detectorChapter 7Finite state machine designState-machine designAttendant call system Set the statesstate diagramstate/output tableTransition tableEncode for statesAttendant call system Attendant call system Minimal cost design with DFFQRCQD*When A
2、 changes from 0 to 1,One-clock-cycle pulse will be generated!Rising-edge detector Set states s0 A=0 Y=0 s1 A=1 Y=1 s2 A=1 Y=0Rising-edge detector State/output tableRising-edge detectorState assignmentTransition tableMinimal cost design with DFF01*11QAQAQD 0 1*00QQAQD0QY Rising-edge detectorRisk chec
3、k:equation-table-state diagram01*11QAQAQD 0 1*00QQAQDSystem will return to valid state from invalid state automaticallyRising-edge detectorMinimal cost design with DFFAQD*111*00QAQD 01 QQYCan we do it better?Rising-edge detectorMinimal cost design with DFFAQD*11 1*00QAQD0QY Even better?Rising-edge detectorMinimal cost design with DFFAQD*11 1*00QAQD0QY Design of Counters A Moore machine with single state circle.Q:states output;RCO:last state.
