1、先进芯片封装知识介绍先进芯片封装知识介绍2020/11/302Outline Package Development Trend 3D Package WLCSP&Flip Chip Package2020/11/303Package Development Trend2020/11/304 SO Family QFP Family BGA FamilyPackage Development Trend2020/11/305 CSP Family Memory Card SiP ModulePackage Development Trend2020/11/3063D Package3D Pac
2、kage2020/11/3073D Package IntroductionetCSP StackFunctional IntegrationHighLowTape-SCSP(or LGA)S-CSP(or LGA)S-PBGAS-M2CSPStacked-SiP2 Chip StackWirebond2 Chip StackFlip Chip&WirebondMulti ChipStackPackage onPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP 3 S-CSPS-etCSPetCSP+S-CSP PS
3、-fcCSP+SCSP PoP with interposerFS-CSP2FS-CSP1Paper ThinPS-vfBGA+SCSPPiP 5SCSPSS-SCSP(paste)Ultra thin StackD2D3D4D2D2D3D4D2 PoP QFN4SS-SCSP2020/11/308Stacked DieTop dieBottom dieFOW materilWire2020/11/309TSV TSV(Through Silicon Via)A through-silicon via(TSV)is a vertical electrical connection(via)pa
4、ssing completely through a silicon wafer or die.TSV technology is important in creating 3D packages and 3D integrated circuits.A 3D package(System in Package,Chip Stack MCM,etc.)contains two or more chips(integrated circuits)stacked vertically so that they occupy less space.In most 3D packages,the s
5、tacked chips are wired together along their edges.This edge wiring slightly increases the length and width of the package and usually requires an extra“interposer”layer between the chips.In some new 3D packages,through-silicon via replace edge wiring by creating vertical connections through the body
6、 of the chips.The resulting package has no added length or thickness.Wire Bonding Stacked DieTSV2020/11/3010 Whats PoP?PoP is Package on Package Top and bottom packages are tested separately by device manufacturer or subcon.PoP2020/11/3011PoPPS-vfBGAPS-etCSPLow Loop WirePin Gate MoldPackage Stacking
7、Wafer Thinning PoP Core Technology2020/11/3012PoP Allows for warpage reduction by utilizing fully-molded structure More compatible with substrate thickness reduction Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size/package size ratio Compa
8、tible with flip chip,wire bond,or stacked die configurations Cost effective compared to alternative next generation solutions Amkors TMV PoP Top viewBottom viewThrough Mold Via2020/11/3013PoP Ball Placement on top surface Ball Placement on bottom Die Bond Mold(Under Full optional)Laser drilling Sing
9、ulation Final Visual InspectionBase MtlThermal effect Process Flow of TMV PoP2020/11/3014 Digital(Btm die)+Analog(Middle die)+Memory(Top pkg)Potable Digital Gadget Cellular Phone,Digital Still Camera,Potable Game UnitMemory dieAnalog dieDigital diespacerEpoxyPiP2020/11/3015Easy system integrationFle
10、xible memory configuration100%memory KGDThinner package than POPHigh IO interconnection than POPSmall footprint in CSP formatIt has standardball size and pitchConstructed with:Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnection Mold encapsulation Why PiP?PiP2020/11/3
11、016Material for High Reliability Based on Low WarpageWafer ThinningFine Process Control Top Package Attach Die Attach etcOptimized Package DesignFlip ChipUnder-fillTop epoxyISM PiP Core TechnologyPiP2020/11/3017Memory PKGSubstrateFlip chipMemory PKGFlip chipInner PKGAnalogAnalogSpacerDigitalInner PK
12、GWB PIPFC PIPPiP PiP W/B PiP and FC PiP2020/11/3018WLCSP&Flip Chip Package2020/11/3019WLCSP What is WLCSP?WLCSP(Wafer Level Chip Scale Packaging),is not same as traditional packaging method(dicing packaging testing,package size is at least 20%increased compared to die size).WLCSP is packaging and te
13、sting on wafer base,and dicing later.So the package size is exactly same as bare die size.WLCSP can make ultra small package size,and high electrical performance because of the short interconnection.2020/11/3020WLCSP Why WLCSP?Smallest package size:WLCSP have the smallest package size against die si
14、ze.So it has widely use in mobile devices.High electrical performance:because of the short and thick trace routing in RDL,it gives high SI and reduced IR drop.High thermal performance:since there is no plastic or ceramic molding cap,heat from die can easily spread out.Low cost:no need substrate,only
15、 one time testing.WLCSPs disadvantageBecause of the die size and pin pitch limitation,IO quantity is limited(usually less than 50pins).Because of the RDL,stagger IO is not allowed for WLCSP.2020/11/3021RDL RDL:Redistribution Layer A redistribution layer(RDL)is a set of traces built up on a wafers ac
16、tive surface to re-route the bond pads.This is done to increase the spacing between each interconnection(bump).2020/11/3022WLCSP Process Flow of WLCSP2020/11/3023WLCSP Process Flow of WLCSP2020/11/3024Flip Chip PackageFCBGA(Passive Integrated Flip Chip BGA)(PI)-EHS-FCBGA(Passive Integrated Exposed H
17、eat Sink Flip Chip BGA)(PI)-EHS2-FCBGA(Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA)MCM-FCBGA(Multi-Chip-Module FCBGA)PI-EHS-MP-FCBGA(Passive Integrated Exposed Heat Sink Multi Package Flip Chip)2020/11/3025Bump2020/11/3026Bump Development2020/11/3027Bump Development2020/11/3028Bum
18、p Development2020/11/3029C4 Flip Chip Whats C4 Flip Chip?C4 is:Controlled Collapsed Chip Connection Chip is connected to substrate by RDL and Bump Bump material type:solder,gold2020/11/3030C4 Flip Chip BGA Main Features Ball Pitch:0.4mm-1.27mm Package size:up to 55mmx55mm Substrate layer:4-16 Layers
19、 Ball Count:up to 2912 Target Market:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、and DSP etc.Main Benefits Reduced Signal Inductance Reduced Power/Ground Inductance Higher Signal Density Die Shrink&Reduced Package Footprint High Speed and High thermal support2020/11/3031C2 Flip Chip Whats C2 F
20、lip Chip?C2 is:Chip Connection Chip is connected to substrate by copper post Bump material type:copper post with solder platingSilicon DieCopper postSolder2020/11/3032C2 Flip Chip Process Flow of C22020/11/3033C2 Flip Chip Comparison:C2 Vs C4In some cases,C2 can replace C4 or wire bonding package.谢谢！
