1、 9.Introduction to VHDL 9.1 A simple example in VHDL 9.2 Stylistic issues 9.3 The IEEE library 9.4 Conditionals in VHDL 9.5 Handling multi-bit signals 1 9.1 A simple example in VHDL1.EntityWe will start off with a NAND gate.The first thing is to say what the device looks like to the outside world.Th
2、is basically means describing its port map,i.e.the signals that flow in and out of it.2 9.1 A simple example in VHDLTo describe this in VHDL,we use an entity declaration.ENTITY nandgate IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END;Each of the signals in the port map is declared as having a mode and
3、 a type.The mode can be IN or OUT,and simply says whether the signal is an input or an output.3 9.1 A simple example in VHDLThe type STD_LOGIC represents a signal that bit can a value of 0,1,X or U.STD_LOGIC is the normal way to describe logic signals that appear at the input or output of gates,or a
4、t wires in between them.X means unknownU means uninitialized,i.e.a signal that has not yet been assigned any valid logical value.4 9.1 A simple example in VHDL2.Architecture Now that we have described the inputs and outputs,we need to say what the device does,i.e.how its outputs respond to its input
5、s.ARCHITECTURE simple OF nandgate ISBEGIN c=a NAND b;END;The ARCHITECTURE statement says what goes on inside nandgate.5 9.1 A simple example in VHDLAfter the ARCHITECTURE statement comes the word BEGIN.This introduces the main body of the architecture,which explains how the outputs relate to the inp
6、uts.At the end of the body comes the END statement,which says that we have reached the end of the body.How the outputs relate to the inputs is described by c=a NAND b;The symbol=means that the signal c gets the value of a NANDed together with the value of b.Whenever a or b change their value,this st
7、atement causes the value of c to be updated.6 9.1 A simple example in VHDLIf we want to check that our description is functioning correctly,we can feed it into a simulator,a program that predicts how the outputs would change in response to changes in the input.7 9.1 A simple example in VHDL3.BEGIN a
8、nd END statementsVHDL uses the keywords BEGIN and END to indicate the beginning and end of a block respectively.4.SemicolonsVHDL uses the semicolon to indicate the end of a statement.8 9.2 Stylistic issues1.CaseVHDL is not case sensitive.2.Spaces and indents Any number of spaces can be used between
9、words without affecting the meaning of the code.3.Returns Putting in a carriage return makes no difference to the function of the code.9 9.2 Stylistic issues4.Annotating END statementsIn a long description,in order to keep track,we can put the name of what we intend to end after the END statement.EN
10、TITY nandgate IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY nandgate;ARCHITECTURE simple OF nandgate ISBEGIN c=a NAND b;END ARCHITECTURE simple;10 9.2 Stylistic issues5.CommentsComments are text that we introduce into the VHDL description in order to help a person reading to the code to under
11、stand what is happening.Comments are introduced by two dashes.Everything between the two dashes and the end of line is regarded as a comment.11 9.3 The IEEE library1.Opening libraries A large number of features and extensions to the capabilities of the VHDL language are bundled into a library called
12、“IEEE”.The IEEE library is made available by the statement:LIBRARY IEEE;The IEEE library contains many sub-libraries,which in turn contain many features.VHDL sub-libraries are called packages.12 9.3 The IEEE libraryIn order to say which features of which packages we wish to access,we use:USE IEEE.XX
13、XX.YYYYXXXX is the name of the required package YYYY is the name of the specific feature that is to be usedUSE IEEE.XXXX.ALL Often we simply make all features within a package visible by using the VHDL keyword ALL:13 9.3 The IEEE library2.Using STD_LOGIC The standard logic definitions are held in a
14、sub-library called std_logic_1164.The full listing for a NAND gate is:LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY nandgate IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY nandgate;ARCHITECTURE simple OF nandgate ISBEGIN c=a NAND b;END ARCHITECTURE simple;14 9.4 Conditionals in VHDLSometimes
15、 we want to assign a signal in a way that is conditional on something else happening.Exp1:This device is called equals.It has two inputs a and b and one output c.If the two inputs are equal then the output is 1.If the two inputs are unequal,then the output is 0.15 9.4 Conditionals in VHDLLIBRARY iee
16、e;USE ieee.std_logic_1164.ALL;ENTITY equals IS PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY equals;ARCHITECTURE number1 OF equals ISBEGIN c=1 WHEN a=b ELSE 0;END ARCHITECTURE number1;The VHDL description 16 9.5 Handling multi-bit signals1.STD_LOGIC_VECTORs STD_LOGIC_VECTOR can be thought as an
17、array of STD_LOGIC signals.Exp2:Use VHDL to describe the quadruple 2-input OR gate.17 9.5 Handling multi-bit signalsLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY orgate IS PORT(a,b:IN STD_LOGIC_VECTOR(0 TO 3);c:OUT STD_LOGIC_VECTOR(0 TO 3);END ENTITY orgate;ARCHITECTURE number OF orgate ISBEGIN c=
18、a OR b;END ARCHITECTURE number;18 9.5 Handling multi-bit signals2.STD_LOGIC_VECTOR values The value of an STD_LOGIC is indicated by a 0,1,X or U enclosed in single quotes.Assignment statement is:a=1;The value of an STD_LOGIC_VECTOR is indicated by a string of values enclosed in double quotes.Assignm
19、ent statement is:a=”1110”;19 9.5 Handling multi-bit signals3.AggregatesAnother way to specify the value of a STD_LOGIC_VECTOR is to use an aggregate.An aggregate is a group values,separated by commas.a=(1,1,1,0);20 9.5 Handling multi-bit signals（1）Positional assignmenta 1,0=1,3=0,2=1);the 0th value
20、listed goes in the 0th position,the first goes in the first position and so on.（2）Named association 21 9.5 Handling multi-bit signals4.Direction of numbering a:STD_LOGIC_VECTOR(0 TO 3)If a is declared as:As a result,the individual bit positions within a are numbered as 22 9.5 Handling multi-bit sign
21、als5.Arithmetic on STD_LOGIC_VECTORsExp3:It has two inputs,a and b,both of which represent four-bit binary numbers.There is a single one-bit output g,which represents the“greater than”condition.When ab then g=1;otherwise g=0.The way that VHDL handles this is by having two different types of STD_LOGI
22、C_VECTOR.These are called SIGNED and UNSIGNED.23 9.5 Handling multi-bit signalsLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY comp IS PORT(a,b:IN SIGNED(3 DOWNTO 0);g:OUT STD_LOGIC);END ENTITY comp;ARCHITECTURE simple OF comp ISBEGIN g b ELSE 0;END ARCHITECTURE simple;2
23、4 9.5 Handling multi-bit signalsExp4:The device has two inputs,a and b,each of which are 16 bits wide.The 16-bit output c is produced by some arithmetic or logical operation on the two inputs.The operation performed on a and b to produce c depends on the value presented at the opcode input.a AND b11a OR b10a-b01a+b00operationopcode25
