VHDL设计方法new-课件.ppt

1、用VHDL语言实现可编程数字系统设计lVHDL概述lVHDL的设计单元lVHDL的基本语法结构VHDL 概述VHSIC(Very High Speed Integrated Circuit)HardwareDescriptionLanguagelVHDL“告诉我你想要电路做什么，我给你提供能实现这个功能的硬件电路”lVerilog和VHDL类似lABEL、AHDL“告诉我你想要什么样的电路，我给你提供这样的电路”VHDLLibrarySynthesisCompilerVHDLModelTechnologyLibraryNetlistTestVectorsSimulationTiming Ana

2、lysisPlace/RouteText OutputWaveformVHDLLibrarySimulationCompilerVHDLModelVHDLTestBenchSimulationModelTestVectorsVHDLSimulationText OutputWaveformVHDL的设计单元lEntity(实体实体)用来说明模型的外部输入输出特征用来说明模型的外部输入输出特征lArchitecture(构造体构造体)用来定义模型的内容和功能用来定义模型的内容和功能l每一个构造体必须有一个实体与它相对应，所每一个构造体必须有一个实体与它相对应，所以两者一般成对出现以两者一般成对出

3、现l类似一个类似一个“黑盒黑盒”，实体描述了，实体描述了“黑盒黑盒”的输的输入输出口入输出口Entitymy_designd11:0oeclkad11:0a11:0intasmy_designd11:0oeclkad11:0a11:0intasInput 1Input nOutput 1Output nl信号在信号在Package、Entity、Architecture 中声明中声明LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY simp ISPORT(a,b,c,d:IN Std_Logic;g:OUT Std_Logic);END simp;

4、ARCHITECTURE logic OF simp ISSIGNAL e，f:Std_Logic;BEGINe=a or b;f=not(c or d);g=e and f;END logic;LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY if_case IS PORT(a,b,c,d:IN Std_Logic;sel:IN Std_Logic_Vector(1 downto 0);y,z:OUT Std_Logic);END if_case;ARCHITECTURE logic OF if_case ISBEGINif_label:PROC

5、ESS(a,b,c,d,sel)BEGINIF sel=00 THEN y=a;ELSIF sel=01 THEN y=b;ELSIF sel=10 THEN y=c;ELSE y z z z z z=0;END CASE;END PROCESS case_label;END logic;ARCHITECTURE reg1 OF reg1 ISSIGNAL a,b:BIT;BEGINPROCESS(clk)BEGINIF rising_edge(clk)THENa=d;b=a;q=b;END IF;END PROCESS;END reg1;ENTITY reg1 IS PORT(d:in BI

6、T;clk:in BIT;q:out BIT);END reg1;ARCHITECTURE reg1 OF reg1 ISSIGNAL a,b:BIT;BEGINPROCESS(clk)BEGINIF rising_edge(clk)THENa=d;b=a;END IF;END PROCESS;q=b;END reg1;ENTITY reg1 IS PORT(d:in BIT;clk:in BIT;q:out BIT);END reg1;ARCHITECTURE reg1 OF reg1 ISVARIABLE a,b:BIT;BEGINPROCESS(clk)BEGINIF rising_ed

7、ge(clk)THENa=d;b=a;q=b;END IF;END PROCESS;END reg1;l变量在IF语句中被赋值，以用来表示随时钟的变化，不会产生触发器l变量只代表临时存储，不反映实际硬件l变量可用在表示一数据立即变化的表达式中，然后再将变量的值赋给信号基本格式基本格式：LOOP标号标号:重复模式重复模式 LOOP顺序语句；顺序语句；END LOOP LOOP标号标号WHILE LOOP顺序语句顺序语句END LOOP;FOR IN LOOP顺序语句顺序语句END LOOP;LOOP标号标号:LOOP顺序语句顺序语句EXIT LOOP标号标号;END LOOP;NEXT LOOP

8、标号标号 WHEN 语句语句LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITY shift4 ISPORT(shft_lft:in std_logic;d_in:in std_logic_vector(3 downto 0);q_out:out std_logic_vector(7 downto 0);END shift4;ARCHITECTURE logic OF shift4 ISBEGINPROCESS(d_in,shft_lft)VARIABLE shft_var:std_log

9、ic_vector(7 DOWNTO 0);BEGINshft_var(7 downto 4):=0000;shft_var(3 downto 0):=d_in;IF shft_lft=1 THENFOR i IN 7 DOWNTO 4 LOOPshft_var(i):=shft_var(i-4);END LOOP;shft_var(3 downto 0):=“0000”;ELSE shft_var:=shft_var;END IF;q_out=shft_var;END PROCESS;END logic;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENT

10、ITY compare IS PORT(a,b:IN std_logic_vector(0 TO 3);aeqb:OUT std_logic);END compare;ARCHITECTURE archcompare OF compare ISBEGINaeqb=NOT(a(0)XOR b(0)OR (a(1)XOR b(1)OR (a(2)XOR b(2)OR (a(3)XOR b(3);END archcompare;acbbcaLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY dff_a IS PORT(d:in std_logic;clk:

11、in std_logic;q:out std_logic);END dff_a;ARCHITECTURE behavior OF dff_a ISBEGINPROCESS(clk)BEGINIF clkevent and clk=1 THEN q=d;END IF;END PROCESS;END behavior;ARCHITECTURE behavior OF dff_clr ISBEGINPROCESS(clk,clr)BEGINIF clr=0 THEN q=0;ELSIF rising_edge(clk)THEN q=d;END IF;END PROCESS;END behavior;

12、LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ARCHITECTURE logic OF count_a ISBEGINPROCESS(rst,clk)VARIABLE tmp_q:std_logic_vector(15 downto 0);BEGINIF rst=0 THEN q=0;ELSIF rising_edge(clk)THENIF updn=1 THEN tmp_q:=tmp_q+1;ELSE tmp_q:=tmp_q-1;END IF;q=tmp_q;END IF;END PROC

13、ESS;END logic;ENTITY ldcnt IS PORT(clk,ld,oe:IN std_logic;count:INOUT std_logic_vector(7 DOWNTO 0);END ldcnt;ARCHITECTURE archldcnt OF ldcnt ISSIGNAL int_count:std_logic_vector(7 DOWNTO 0);BEGINcnt:PROCESS(clk)BEGINIF rising_edge(clk)THENIF ld=1 THEN int_count=count;ELSE int_count=int_count+1;END IF

14、;END IF;END PROCESS cnt;outen:PROCESS(oe,int_count)BEGINIF oe=1 THEN count=int_count;ELSE count Z);END IF;END PROCESS outen;END archldcnt;RESET(asynchronous)REDTIMER1YELLOWGREENTIMER1TIMER2TIMER2Y=1G=1TIMER3TIMER3R=1InputsNextStateLogicStateRegistersOutputLogicOutputsPresent StateNext StatetcoARCHIT

15、ECTURE arch_2 OF state_machine ISTYPE traffic_states IS(red,yellow,green);SIGNAL sm:traffic_states;BEGINfsm:PROCESS(clock,reset)BEGIN IF reset=1 THEN sm=red;r=1;g=0;y IF timer1=1 THEN sm=green;r=0;g=1;y=0;ELSE sm=red;r=1;g IF timer2=1 THEN sm=yellow;r=0;g=0;y=1;ELSE sm=green;r=0;g=1;y IF timer3=1 TH

16、EN sm=red;r=1;g=0;y=0;ELSE sm=yellow;r=0;g=0;y sm=red;END CASE;END IF;END PROCESS fsm;END arch_2;OutputsStateRegistersOutputLogicOutputRegistersInputsNextStateLogicPresent StatetcoARCHITECTURE arch_3 OF state_machine ISSIGNAL sm:std_logic_vector(2 DownTo 0);Constant red:std_logic_vector(2 DownTo 0):

17、=”100;Constant green:std_logic_vector(2 DownTo 0):=010;Constant yellow:std_logic_vector(2 DownTo 0):=001;BEGIN fsm:PROCESS(clock,reset)BEGIN IF reset=1 THEN sm IF timer1=1 THEN sm=green;ELSE sm IF timer2=1 THEN sm=yellow;ELSE sm IF timer3=1 THEN sm=red;ELSE sm sm=red;END CASE;END IF;END PROCESS fsm;

18、r=sm(2);g=sm(1);y=sm(0);END arch_3;StateRegistersOutputsInputsLogicbselmux2to1accbmux2to1aselsymbolcomponent schematic entity/architecturelibrarypackagetop level schematictop level entity/architecturertoplevelqscbmux2to1aseltpYour Design(VHDL)LIBRARY ieee;USE ieee.std_logic_1164.USE cypress.std_arit

19、h.allLibrary(Compiled)ieeeLibrary(Compiled)AlteraPackages(VHDL)Others(VHDL)std_logictypedefinitionsOthers(VHDL)overloadedoperatorsPackages(VHDL)std_logic_1164std_arithLIBRARY ieee;USE ieee.std_logic_1164.ALL;PACKAGE mymuxpkg ISCOMPONENT mux2to1 PORT(a,b,sel:IN std_logic;c:OUT std_logic);END COMPONEN

20、T;END mymuxpkg;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY mux2to1 IS PORT(a,b,sel:IN std_logic;c:OUT std_logic);END mux2to1;ARCHITECTURE archmux2to1 OF mux2to1 ISBEGIN c i(2),b=r(0),sel=s,c=t(0);m1:mux2to1 PortMap(c=t(1),b=r(1),a=i(1),sel=s);i=p AND NOT q;END archtoplevel;lMax+Plus II 支持 VHDL87

21、 和VHDL93lMax+Plus II 只提供这两个 IEEE 标准的子集l详细信息可参考Altera的VHDL手册单击单击图标图标l编译VHDL文件I forgot.If-then-elsecase-end caseloop-end loop?Use this symbol just as you use 7400MatchSerial_inclkVHDL State Machinelibrary ieee;use ieee.std_logic_1164.all;package your_own_type istype t_state is(idle,state0,state01,stat

22、e011,state0110,state01101,state011011);end your_own_type;library ieee;use ieee.std_logic_1164.all;use work.your_own_type.all;Entity stmh isport(clk,serial_in,reset:in std_logic;match:out std_logic);end stmh;architecture body_stmh of stmh issignal present_state:t_state;beginprocess(clk,serial_in,pres

23、ent_state)beginif(reset=1)thenpresent_state if(serial_in=1)then present_state=state011011;else present_state present_state present_state=idle;end case;end if;end if;end process;process(present_state)beginif(present_state=state011011)thenmatch=1;elsematch if(serial_in=0)then present_state=state0;else

24、 present_state if(serial_in=1)then present_state=state01;else present_state if(serial_in=1)then present_state=state011;else present_state if(serial_in=0)then present_state=state0110;else present_state if(serial_in=1)then present_state=state01101;else present_state if(serial_in=0)then present_state=s

25、tate0;else present_state if(serial_in=0)then next_state=state0;match=0;else next_state=idle;match if(serial_in=1)then next_state=state01;match=0;else next_state=idle;match if(serial_in=1)then next_state=state011;match=0;else next_state=idle;match if(serial_in=0)then next_state=state0110;match=0;else

26、 next_state=idle;match if(serial_in=1)then next_state=state01101;match=0;else next_state=idle;match if(serial_in=1)then next_state=state011011;match=1;else next_state=idle;match next_state=idle;match next_state=idle;match=0;end case;end if;end process;present_state if(serial_in=0)then next_state=sta

27、te0;match=0;else next_state=idle;match if(serial_in=1)then next_state=state01;match=0;else next_state=idle;match if(serial_in=1)then next_state=state011;match=0;else next_state=idle;match if(serial_in=0)then next_state=state0110;match=0;else next_state=idle;match if(serial_in=1)then next_state=state01101;match=0;else next_state=idle;match if(serial_in=1)then next_state=state011011;match=1;else next_state=idle;match next_state=idle;match next_state=idle;match=0;end case;end if;end process;end body_stmh;