1、Lecture 0:IntroductionCMOS VLSI Design 4th Ed.0:Introduction2Introductionq Integrated circuits:many transistors on one chip.q Very Large Scale Integration(VLSI):bucketloads!q Complementary Metal Oxide Semiconductor Fast,cheap,low power transistorsq Today:How to build your own simple CMOS chip CMOS t
2、ransistors Building logic gates from transistors Transistor layout and fabricationq Rest of the course:How to build a good CMOS chipCMOS VLSI Design 4th Ed.0:Introduction3Silicon Latticeq Transistors are built on a silicon substrateq Silicon is a Group IV materialq Forms crystal lattice with bonds t
3、o four neighborsSiSiSiSiSiSiSiSiSiCMOS VLSI Design 4th Ed.0:Introduction4Dopantsq Silicon is a semiconductorq Pure silicon has no free carriers and conducts poorlyq Adding dopants increases the conductivityq Group V:extra electron(n-type)q Group III:missing electron,called hole(p-type)AsSiSiSiSiSiSi
4、SiSiBSiSiSiSiSiSiSiSi-+-CMOS VLSI Design 4th Ed.0:Introduction5p-n Junctionsq A junction between p-type and n-type semiconductor forms a diode.q Current flows only in one directionp-typen-typeanodecathodeCMOS VLSI Design 4th Ed.0:Introduction6nMOS Transistorq Four terminals:gate,source,drain,bodyq G
5、ate oxide body stack looks like a capacitor Gate and body are conductors SiO2(oxide)is a very good insulator Called metal oxide semiconductor(MOS)capacitor Even though gate is no longer made of metalCMOS VLSI Design 4th Ed.0:Introduction7nMOS Operationq Body is usually tied to ground(0 V)q When the
6、gate is at a low voltage:P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows,transistor is OFFCMOS VLSI Design 4th Ed.0:Introduction8nMOS Operation Cont.q When the gate is at a high voltage:Positive charge on gate of MOS capacitor Negative charge attracted to bod
7、y Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain,transistor is ONCMOS VLSI Design 4th Ed.0:Introduction9pMOS Transistorq Similar,but doping and voltages reversed Body tied to high voltage(VDD)Gate low:transistor ON Gate high:tr
8、ansistor OFF Bubble indicates inverted behaviorCMOS VLSI Design 4th Ed.0:Introduction10Power Supply Voltageq GND=0 Vq In 1980s,VDD=5Vq VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves powerq VDD=3.3,2.5,1.8,1.5,1.2,1.0,CMOS VLSI Design 4th Ed.0:Intr
9、oduction11Transistors as Switchesq We can view MOS transistors as electrically controlled switchesq Voltage at gate controls path from source to draingsdg=0sdg=1sdgsdsdsdnMOSpMOSOFFONONOFFCMOS VLSI Design 4th Ed.0:Introduction120CMOS InverterAY0110AYOFFON 1ONOFFCMOS VLSI Design 4th Ed.0:Introduction
10、13CMOS NAND GateABY001011101110OFFOFFONON11OFFON OFFON01ON OFFONOFF10ON ON OFFOFF00ABYCMOS VLSI Design 4th Ed.0:Introduction14CMOS NOR GateABY001010100110ABYCMOS VLSI Design 4th Ed.0:Introduction153-input NAND Gateq Y pulls low if ALL inputs are 1q Y pulls high if ANY input is 0ABYCCMOS VLSI Design
11、4th Ed.0:Introduction16CMOS Fabricationq CMOS transistors are fabricated on silicon waferq Lithography process similar to printing pressq On each step,different materials are deposited or etchedq Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing proce
12、ssCMOS VLSI Design 4th Ed.0:Introduction17Inverter Cross-sectionq Typically use p-type substrate for nMOS transistorsq Requires n-well for body of pMOS transistorsCMOS VLSI Design 4th Ed.0:Introduction18Well and Substrate Tapsq Substrate must be tied to GND and n-well to VDDq Metal to lightly-doped
13、semiconductor forms poor connection called Shottky Diodeq Use heavily doped well and substrate contacts/tapsCMOS VLSI Design 4th Ed.0:Introduction19Inverter Mask Setq Transistors and wires are defined by masksq Cross-section taken along dashed lineCMOS VLSI Design 4th Ed.0:Introduction20Detailed Mas
14、k Viewsq Six masks n-well Polysilicon n+diffusion p+diffusion Contact MetalCMOS VLSI Design 4th Ed.0:Introduction21Fabricationq Chips are built in huge factories called fabsq Contain clean rooms as large as football fieldsCourtesy of InternationalBusiness Machines Corporation.Unauthorized use not pe
15、rmitted.CMOS VLSI Design 4th Ed.0:Introduction22Fabrication Stepsq Start with blank waferq Build inverter from the bottom upq First step will be to form the n-well Cover wafer with protective layer of SiO2(oxide)Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafe
16、r Strip off SiO2p substrateCMOS VLSI Design 4th Ed.0:Introduction23Oxidationq Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnacep substrateSiO2CMOS VLSI Design 4th Ed.0:Introduction24Photoresistq Spin on photoresist Photoresist is a light-sensitive organic polymer Softens wh
17、ere exposed to lightp substrateSiO2PhotoresistCMOS VLSI Design 4th Ed.0:Introduction25Lithographyq Expose photoresist through n-well maskq Strip off exposed photoresistp substrateSiO2PhotoresistCMOS VLSI Design 4th Ed.0:Introduction26Etchq Etch oxide with hydrofluoric acid(HF)Seeps through skin and
18、eats bone;nasty stuff!q Only attacks oxide where resist has been exposedp substrateSiO2PhotoresistCMOS VLSI Design 4th Ed.0:Introduction27Strip Photoresistq Strip off remaining photoresist Use mixture of acids called piranah etchq Necessary so resist doesnt melt in next stepp substrateSiO2CMOS VLSI
19、Design 4th Ed.0:Introduction28n-wellq n-well is formed with diffusion or ion implantationq Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Siq Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO2,only enter exposed Sin wellSiO2CMOS VLSI D
20、esign 4th Ed.0:Introduction29Strip Oxideq Strip off the remaining oxide using HFq Back to bare wafer with n-wellq Subsequent steps involve similar series of stepsp substraten wellCMOS VLSI Design 4th Ed.0:Introduction30Polysiliconq Deposit very thin layer of gate oxide 20 (6-7 atomic layers)q Chemic
21、al Vapor Deposition(CVD)of silicon layer Place wafer in furnace with Silane gas(SiH4)Forms many small crystals called polysilicon Heavily doped to be good conductorCMOS VLSI Design 4th Ed.0:Introduction31Polysilicon Patterningq Use same lithography process to pattern polysiliconCMOS VLSI Design 4th
22、Ed.0:Introduction32Self-Aligned Processq Use oxide and masking to expose where n+dopants should be diffused or implantedq N-diffusion forms nMOS source,drain,and n-well contactCMOS VLSI Design 4th Ed.0:Introduction33N-diffusionq Pattern oxide and form n+regionsq Self-aligned process where gate block
23、s diffusionq Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processingCMOS VLSI Design 4th Ed.0:Introduction34N-diffusion cont.q Historically dopants were diffusedq Usually ion implantation todayq But regions are still called diffusionCMOS VLSI Design 4th
24、 Ed.0:Introduction35N-diffusion cont.q Strip off oxide to complete patterning stepCMOS VLSI Design 4th Ed.0:Introduction36P-Diffusionq Similar set of steps form p+diffusion regions for pMOS source and drain and substrate contactCMOS VLSI Design 4th Ed.0:Introduction37Contactsq Now we need to wire to
25、gether the devicesq Cover chip with thick field oxideq Etch oxide where contact cuts are neededContactCMOS VLSI Design 4th Ed.0:Introduction38Metalizationq Sputter on aluminum over whole waferq Pattern to remove excess metal,leaving wiresMetalCMOS VLSI Design 4th Ed.0:Introduction39Layoutq Chips are
26、 specified with set of masksq Minimum dimensions of masks determine transistor size(and hence speed,cost,and power)q Feature size f=distance between source and drain Set by minimum width of polysiliconq Feature size improves 30%every 3 years or soq Normalize for feature size when describing design r
27、ulesq Express rules in terms of l=f/2 E.g.l=0.3 mm in 0.6 mm processCMOS VLSI Design 4th Ed.0:Introduction40Simplified Design Rulesq Conservative rules to get you startedCMOS VLSI Design 4th Ed.0:Introduction41Inverter Layoutq Transistor dimensions specified as Width/Length Minimum size is 4l/2l,som
28、etimes called 1 unit In f=0.6 mm process,this is 1.2 mm wide,0.6 mm longCMOS VLSI Design 4th Ed.0:Introduction42Summaryq MOS transistors are stacks of gate,oxide,siliconq Act as electrically controlled switchesq Build logic gates out of switchesq Draw masks to specify layout of transistorsq Now you
29、know everything necessary to start designing schematics and layout for a simple chip!CMOS VLSI Design 4th Ed.0:Introduction43About these Notesq Lecture notes 2010 David Money Harrisq These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.CMOS VLSI Design 4th Ed.祝您成功！
