1、第六讲 复杂电路的描述方法ECE 545 Introduction to VHDLVHDL for SpecificationVHDL for SimulationVHDL for SynthesisECE 545 Introduction to VHDLLevels of design descriptionAlgorithmic levelRegister Transfer LevelLogic(gate)levelCircuit(transistor)levelPhysical(layout)levelLevel of description most suitable for synt
2、hesisECE 545 Introduction to VHDLRegister Transfer Logic(RTL)Design Description Combinational Logic Combinational LogicRegistersTodays TopicECE 545 Introduction to VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral Registers State mac
3、hines Test benchesSequential statementsSubset most suitable for synthesis VHDLVHDL的执行语句的执行语句描述结构体中电路硬件的变化特点；描述结构体中电路硬件的变化特点；结构体中的任何执行语句都是并行语句；结构体中的任何执行语句都是并行语句；并行语句的种类有：并行语句的种类有：赋值类语句：数据流描述赋值类语句：数据流描述 (逻辑函数的运算逻辑函数的运算)元件类语句：结构描述元件类语句：结构描述 （逻辑符号的连接）（逻辑符号的连接）进程语句：行为描述进程语句：行为描述 （电路功能的流程）（电路功能的流程）ECE 545
4、 Introduction to VHDLXOR3 ExampleECE 545 Introduction to VHDLEntity(XOR3 Gate)entity XOR3 is port(A:in STD_LOGIC;B:in STD_LOGIC;C:in STD_LOGIC;RESULT:out STD_LOGIC );end XOR3;ECE 545 Introduction to VHDLDataflow Architecture(XOR3 Gate)architecture XOR3_DATAFLOW of XOR3 issignal U1_OUT:STD_LOGIC;begi
5、n U1_OUT=A xor B;RESULT A,I2=B,Y =U1_OUT);U2:XOR2 port map(I1=U1_OUT,I2=C,Y =RESULT);end XOR3_STRUCTURAL;I1I2YXOR2ABCRESULTU1_OUTXOR3ABCRESULTXOR3ECE 545 Introduction to VHDLBehavioral Architecture(XOR Gate)architecture XOR3_BEHAVIORAL of XOR3 isbeginXOR3_BEHAVE:process(A,B,C)beginif(A xor B xor C)=
6、1)thenRESULT=1;elseRESULT=0;end if;end process XOR3_BEHAVE;end XOR3_BEHAVIORAL;ECE 545 Introduction to VHDLDataflow Description Describes how data moves through the system and the various processing steps.Data Flow uses series of concurrent statements to realize logic.Concurrent statements are evalu
7、ated at the same time;thus,order of these statements doesnt matter.Data Flow is most useful style when series of Boolean equations can represent a logic.ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment ()conditional concurrent signal assignment (when-else)selected concurrent s
8、ignal assignment (with-select-when)generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment ()conditional concurrent signal assignment (when-else)selected concurrent signal assignment (with-select-when)
9、generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 Introduction to VHDLData-flow VHDL:Example0 0 0 1 0 1 1 1 c i 1+0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 c i x i y i 000111100 1 x i y i c i 1 1 1 1 s i x i y i c i =000111100 1 x i y i c i 1 1 1 1 c i
10、1+x i y i x i c i y i c i+=c i x i y i s i c i 1+(a)Truth table(b)Karnaugh maps(c)Circuit 0 1 1 0 1 0 0 1 s i ECE 545 Introduction to VHDLData-flow VHDL:ExampleLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY fulladd ISPORT(x,y,Cin:IN STD_LOGIC;s,Cout:OUT STD_LOGIC);END fulladd;ARCHITECTURE LogicFunc
11、 OF fulladd ISBEGINs=x XOR y XOR Cin;Cout=(x AND y)OR(Cin AND x)OR(Cin AND y);END LogicFunc;ECE 545 Introduction to VHDLLogic Operators Logic operators Logic operators precedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowestECE 545 Introduction to VHDL Wanted:Y=ab+cdIncorrectY
12、=a and b or c and d equivalent toY=(a and b)or c)and d equivalent toY=(ab+c)dCorrectY=(a and b)or(c and d)No Implied Precedence ECE 545 Introduction to VHDLConcatenationsignal A:STD_LOGIC_VECTOR(3 downto 0);signal B:STD_LOGIC_VECTOR(3 downto 0);signal C,D,E:STD_LOGIC_VECTOR(7 downto 0);A=”0000”;B=”1
13、111”;C=A&B;-C=”00001111”D=0&”0001111”;-D=”00001111”E=0&0&0&0&1&1&1&1;-E=”00001111”ECE 545 Introduction to VHDLRotations in VHDLA(3)A(2)A(1)A(0)A(2)A(1)A(0)A(3)A1A_rotL=A(2 downto 0)&A(3)ECE 545 Introduction to VHDLArithmetic Functions in VHDL(1)To use basic arithmetic operations involving std_logic_
14、vectors you need to include thefollowing library packages:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ECE 545 Introduction to VHDLArithmetic Functions in VHDL(2)You can use standard+,-operatorsto perform addition and subtraction:signal A:STD_LOGIC_VECTOR(3 downto 0);sign
15、al B:STD_LOGIC_VECTOR(3 downto 0);signal C:STD_LOGIC_VECTOR(3 downto 0);C=A+B;ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment ()conditional concurrent signal assignment (when-else)selected concurrent signal assignment (with-select-when)generate scheme for equations (for-gener
16、ate)Major instructionsConcurrent statementsECE 545 Introduction to VHDLData Flow Instructions(1)target_signal=value1 when condition1 else value2 when condition2 else .valueN-1 when conditionN-1 else valueN;When-Else.Value NValue N-1Condition N-1Condition 2Condition 1Value 2Value 1Target SignalECE 54
17、5 Introduction to VHDLOperators Relational operators Logic and relational operators precedence=/=not=/=and or nand nor xor xnorHighestLowestECE 545 Introduction to VHDL compare a=bcIncorrect when a=b and c else equivalent to when(a=b)and c else Correct when a=(b and c)else Priority of logic and rela
18、tional operators ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment ()conditional concurrent signal assignment (when-else)selected concurrent signal assignment (with-select-when)generate scheme for equations (for-generate)Major instructionsConcurrent statementsECE 545 Introducti
19、on to VHDLData Flow Instructions(2)with choice_expression select target_signal=expression1 when choices1,expression2 when choices2,.expressionN when choicesN;With-Selectchoices1choices2choicesNexpression1target_signalchoice expressionexpression2expressionNECE 545 Introduction to VHDLMLU ExampleECE 5
20、45 Introduction to VHDLMLU:Block DiagramBANEG_ANEG_BIN0IN1IN2IN3OUTPUTSEL1SEL0MUX_4_1L0L1NEG_YYY1A1B1MUX_0MUX_1MUX_2MUX_3ECE 545 Introduction to VHDLMLU:Entity Declarationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity MLU is port(NEG_A:in STD_LOGIC;NEG_B:in STD_LOGIC;NEG_Y:in STD_LOGIC;A:in STD_LOG
21、IC;B:in STD_LOGIC;L1:in STD_LOGIC;L0:in STD_LOGIC;Y:out STD_LOGIC );end MLU;ECE 545 Introduction to VHDLMLU:Architecture Declarative Sectionarchitecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0:STD_LOGIC;signal MUX_1:STD_LOGIC;signal MUX_2:STD_LO
22、GIC;signal MUX_3:STD_LOGIC;signal L:STD_LOGIC_VECTOR(1 downto 0);ECE 545 Introduction to VHDLMLU-Architecture BodybeginA1=not A when(NEG_A=1)elseA;B1=not B when(NEG_B=1)else B;Y=not Y1 when(NEG_Y=1)elseY1;MUX_0=A1 and B1;MUX_1=A1 or B1;MUX_2=A1 xor B1;MUX_3=A1 xnor B1;L=L1&L0;with(L)select Y1=MUX_0
23、when 00,MUX_1 when 01,MUX_2 when 10,MUX_3 when others;end MLU_DATAFLOW;ECE 545 Introduction to VHDLData-flow VHDL concurrent signal assignment ()conditional concurrent signal assignment (when-else)selected concurrent signal assignment (with-select-when)generate scheme for equations (for-generate)Maj
24、or instructionsConcurrent statementsECE 545 Introduction to VHDLPARITY ExampleECE 545 Introduction to VHDLPARITY:Block DiagramECE 545 Introduction to VHDLFor Generate StatementFor Generatename:for parameter_specification generate Declaration Statements begin Concurrent Statements end generate name;E
25、CE 545 Introduction to VHDLPARITY:Entity Declarationlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity PARITY is port(Parity_in:in STD_LOGIC_VECTOR(7 downto 0);Parity_out:out STD_LOGIC );end PARITY;ECE 545 Introduction to VHDLPARITY:Block DiagramXor_out(1)Xor_out(2)Xor_out(3)Xor_out(4)Xor_out(5)Xor_out
26、(6)Xor_out(7)ECE 545 Introduction to VHDLPARITY:Architecturearchitecture PARITY_DATAFLOW of PARITY is signal Xor_out:std_logic_vector(7 downto 1);beginXor_out(1)=Parity_in(0)xor Parity_in(1);G2:for i in 1 to 6 generateXor_out(i+1)=Xor_out(i)xor Parity_in(i+1);end generate G2;Parity_out B01 if AB1010
27、 independently of A and B0101 independently of A and B11(invalid inputs)-ECE 545 Introduction to VHDLABX_OUTY_OUTBIT_COMPAREentity BIT_COMPARE is port(A,B,X_IN,Y_IN:in STD_LOGIC;X_OUT,Y_OUT:out STD_LOGIC);end BIT_COMPARE;X_INY_INBasic building blockECE 545 Introduction to VHDLX_IN&Y_INX_OUT&Y_OUT000
28、0 if A=B10 if A=1 and B=001 if A=0 and B=11010 independently of A and B0101 independently of A and B11(invalid inputs)-Basic building block Truth TableECE 545 Introduction to VHDL8-bit comparator-ArchitectureA(7)B(7)CMP_IN(1)CMP_IN(0)A(6)B(6)A(0)B(0)CMP_OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(
29、1)INT_X(6)INT_Y(6)ECE 545 Introduction to VHDLarchitecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A,B,X_IN,Y_IN:in STD_LOGIC;X_OUT,Y_OUT:out STD_LOGIC);end component;signal INT_X,INT_Y:STD_LOGIC_VECTOR(7 downto 1);begin C7:BIT_COMPARE port map(A(7),B(7),CMP_IN(1),CMP_IN(0),INT_X(7),INT_
30、Y(7);C6:BIT_COMPARE port map(A(6),B(6),INT_X(7),INT_Y(7),INT_X(6),INT_Y(6);.C0:BIT_COMPARE port map(A(0),B(0),INT_X(1),INT_Y(1),CMP_OUT(0),CMP_OUT(1);end STRUCTURE;Architecture without for-generateECE 545 Introduction to VHDL8-bit comparator-ArchitectureA(7)B(7)CMP_IN(1)CMP_IN(0)A(6)B(6)A(0)B(0)CMP_
31、OUT(1)CMP_OUT(0)INT_X(7)INT_X(1)INT_Y(7)INT_Y(1)INT_X(8)INT_Y(8)INT_X(0)INT_Y(0)ECE 545 Introduction to VHDLarchitecture STRUCTURE of COMPARE8 is component BIT_COMPARE port(A,B,X_IN,Y_IN:in STD_LOGIC;X_OUT,Y_OUT:out STD_LOGIC);end component;signal INT_X,INT_Y:STD_LOGIC_VECTOR(8 downto 0);begin INT_X
32、(8)=CMP_IN(1);INT_Y(8)=CMP_IN(0);CASCADE:for I in 7 downto 0 generate C:BIT_COMPARE port map(A(I),B(I),INT_X(I+1),INT_Y(I+1),INT_X(I),INT_Y(I);end generate;CMP_OUT(1)=INT_X(0);CMP_OUT(0)=INT_Y(0);end STRUCTURE;Architecture with for-generateECE 545 Introduction to VHDLStructural VHDL component instan
33、tiation (port map)generate scheme for component instantiations (for-generate)component instantiation with generic (generic map,port map)Major instructionsECE 545 Introduction to VHDLN-bit Comparator Entity declarationentity COMPAREN is generic(N:positive);-N width of operands port(A,B:in BIT_VECTOR(
34、N-1 downto 0);CMP_IN:in BIT_VECTOR(1 downto 0);CMP_OUT:out BIT_VECTOR(1 downto 0);end COMPAREN;ECE 545 Introduction to VHDLarchitecture STRUCTURE of COMPAREN is component BIT_COMPARE port(A,B,X_IN,Y_IN:in STD_LOGIC;X_OUT,Y_OUT:out STD_LOGIC);end component;signal INT_X,INT_Y:STD_LOGIC_VECTOR(N downto
35、 0);begin INT_X(N)=CMP_IN(1);INT_Y(N)=CMP_IN(0);CASCADE:for I in N-1 downto 0 generate C:BIT_COMPARE port map(A(I),B(I),INT_X(I+1),INT_Y(I+1),INT_X(I),INT_Y(I);end generate;CMP_OUT(1)=INT_X(0);CMP_OUT(0)16)port map(A=P1,B=P2,CMP_IN=SIG_IN,CMP_OUT=SIG_OUT );N-bit Comparator InstantiationECE 545 Intro
36、duction to VHDLBehavioral Design StyleECE 545 Introduction to VHDLBehavioral VHDL(subset)process statement (process)sequential signal assignment ()Major instructionsSequential statementsGeneralRegisters,counters,shift registers,etc.if-then-else statementState machines case-when statementTestbenches
37、loops (for-loop,while-loop)ECE 545 Introduction to VHDLAnatomy of a Processlabel:process(sensitivity list)declaration partbegin statement partend process;OPTIONALECE 545 Introduction to VHDL A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyw
38、ord BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY.Hence,order of statements is important.A process must end with the keywords END PROCESS.TESTING:process beginTEST_VECTOR=“00”;wait for 10 ns;TEST_VECTOR=“01”;wait for 10 ns;TEST_VECTOR=
39、“10”;wait for 10 ns;TEST_VECTOR=“11”;wait for 10 ns;end process;A process is a sequence of instructions referred to as sequential statements.What is a PROCESS?The Keyword PROCESSECE 545 Introduction to VHDLPROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive.Whenever the
40、re is an event on any of the signals in the sensitivity list,the process fires.Every time the process fires,it will run in its entirety.WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label:process(sensitivity list)declaration part begin statement part end process;ECE 545 Introd
41、uction to VHDLProcesses in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to Be Synthesiz
42、ed Use Processes Freely in TestbenchesECE 545 Introduction to VHDLUse of Processes in the Synthesizable CodeECE 545 Introduction to VHDLComponent Equivalent of a Process All signals which appear on the left of signal assignment statement(=)are outputs e.g.y,z All signals which appear on the right of
43、 signal assignment statement(=)or in logic expressions are inputs e.g.w,a,b,c All signals which appear in the sensitivity list are inputs e.g.clk Note that not all inputs need to be included in the sensitivity listpriority:PROCESS(clk)BEGINIF w(3)=1 THENy=11;ELSIF w(2)=1 THEN y=10;ELSIF w(1)=c THENy
44、=a and b;ELSEz=00;END IF;END PROCESS;wayzprioritybcclkECE 545 Introduction to VHDLRegistersECE 545 Introduction to VHDLClock D 0 1 1 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q Clock ECE 545 Introduction to VHDLClk D 0 1 0 1 Truth table t 1 t
45、2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock Graphical symbol0 Q(t)1 ECE 545 Introduction to VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY latch IS PORT(D,Clock:IN STD_LOGIC;Q:OUT STD_LOGIC);END latch;ARCHITECTURE Behavior OF latch IS BEGINPROCESS(D,Clock)BEGINIF Clock=
46、1 THEN Q=D;END IF;END PROCESS;END Behavior;D latchD Q Clock ECE 545 Introduction to VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY flipflop IS PORT(D,Clock:INSTD_LOGIC;Q:OUT STD_LOGIC);END flipflop;ARCHITECTURE Behavior_1 OF flipflop IS BEGINPROCESS(Clock)BEGIN IF ClockEVENT AND Clock=1 THEN Q=
47、D;END IF;END PROCESS;END Behavior_1;D flip-flopD Q Clock ECE 545 Introduction to VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY flipflop IS PORT(D,Clock:INSTD_LOGIC;Q:OUT STD_LOGIC);END flipflop;ARCHITECTURE Behavior_2 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL ClockEVENT AND Clock=1;Q=D;END P
48、ROCESS;END Behavior_2;D flip-flopD Q Clock ECE 545 Introduction to VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY flipflop IS PORT(D,Resetn,Clock:IN STD_LOGIC;Q:OUT STD_LOGIC);END flipflop;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS(Resetn,Clock)BEGIN IF Resetn=0 THEN Q=0;ELSIF ClockEVENT
49、 AND Clock=1 THEN Q=D;END IF;END PROCESS;END Behavior;D flip-flop with asynchronous resetD Q Clock Resetn ECE 545 Introduction to VHDLLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY flipflop IS PORT(D,Resetn,Clock:IN STD_LOGIC;Q:OUT STD_LOGIC);END flipflop;ARCHITECTURE Behavior OF flipflop IS BEGINP
50、ROCESS BEGIN WAIT UNTIL ClockEVENT AND Clock=1;IF Resetn=0 THEN Q=0;ELSEQ=D;END IF;END PROCESS;END Behavior;D flip-flop with synchronous resetD Q Clock Resetn ECE 545 Introduction to VHDL8-bit register with asynchronous resetLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY reg8 ISPORT(D:IN STD_LOGIC_
