1、信号完整性分析信号完整性分析Signal Integrity 第五讲：过孔、连接器、封装Vias,Connectors,and Packages第五讲:过孔、连接器、封装Suggested Reading:1 S Hall,G Hall,and J McCall,High-Speed Digital System Design:A Handbook of Interconnect Theory and Design Practice,Chapters 5&11 John Wiley&Sons,2000.2 H Johnson and M Graham,High-Speed Digital De
2、sign:A handbook of Black Magic,Chapters 7&9,Prentice Hall,1993.3 B Young,Digital Signal Integrity,Chapter 2,Prentice Hall,2001.How are signal getting from one chip to another?Pentium 4 CPU goes here(socket)Memory ConnectorBridgechipVias,connectors,and packages are all important and necessary parts o
3、f the path.Bridge chip packageTopics Vias Definition:what are they and why do we need them?Electrical models of via parasiticsConnectors Definition:what are they and why do we need them?Electrical effects Inductance SLEM-style approximation Power and ground pins Design considerations(tradeoffs,rules
4、 of thumb)Topics(continued)Packages Definition:what they are and why we need them?Common types(e.g.flip-chip,bondwire)and history Creating package models Effect of a package on signal integrity Design considerationsl Vertical connections between layers made by drilling a small hole and filling it wi
5、th conductive material.Connecting metal layers on silicon chips,within packages,and on printed circuit boards.capacitorchipchipPrinted Circuit BoardViasVias Barrel:conductive cylinder filling the drilled hole Pad:connects the barrel to the component/plane/trace Antipad:clearance hole between via and
6、 no-connect metal layerBarrelPadVia pad does not contact plane;void is the anti-padTrace connected to pad on layer 1.Via:Vertical Connection between LayersPadq Connect metal planes of the same potential(e.g.,all ground planes conductively attached)q Carry a signal from a trace on one layer to anothe
7、r(e.g.,every data signal must get from the silicon bump down to the motherboard)q Connect components(such as a capacitor)to a signal trace or a voltage plane.What Can a Via Do?PCB Via TypesPCB Via Types过孔(Via)l 过孔在多层PCB设计中非常重要，一个过孔主要由三部分组成：1.孔；2.孔周围的焊盘区；3.POWER和GROUND层的隔离区。l 过孔的工艺过程过孔壁圆柱面上用化学沉积的方法镀上
8、一层金属，用以连通中间各层需要连通的铜箔；过孔的上下两面做成普通的焊盘形状，可直接与上下两面的线路相通，也可不连；过孔可以起到电气连接、固定或定位器件的作用。PCB Via Types过孔一般又分为三类：盲孔、埋孔和通孔。l 盲孔指位于印刷线路板的顶层和底层表面，具有一定深度，用于表层线路和下面的内层线路的连接，孔的深度与孔径通常不超过一定的比率。l 埋孔，,指位于印刷线路板内层的连接孔，它不会延伸到线路板的表面。(盲孔与埋孔两类孔都位于线路板的内层，层压前完成。)l 通孔，这种孔穿过整个线路板，可用于实现内部互连或作为元件的安装定位孔,大都是层压后完成。由于通孔在工艺上更易于实现，成本较低，
9、所以一般印制电路板都使用通孔。SEM(Scanning Electronic Micrograph)Cross-Section Images Laser generated viaPhoto-defined viaPlasma generated viaCond.ink filled via激光打孔技术等离子干腐蚀技术More SEM Cross-section ImagesMicroviaPlated-through holeL_barrelC_padC_padl Vias are tiny structures unless Tvia delay 1/10 signal edgel The
10、 via can be modeled as a lumped pi-model.To dark pink t-lineTo pink t-lineEquivalent Circuit Model of a ViaSame as low pass filter Cascading ElementsL_barrelC_padC_padL_barrelC_padTraceconnectionTraceconnectionVia Capacitance Effect is to slow the edge Empirical formula for pad capacitance:Via Induc
11、tance Series L degrades signal integrity Empirical formula for barrel inductance:121411DDTDCrvia.14ln08.5dhhLviaD1:Via pad diameterD2:Via anti-pad diameterT:PCB thicknessh:via lengthd:barrel diameterVia Induced Delay capacitive loading+inductive loading+added distanceExample 1Model parasitics of via
12、s Ladder Model LCs are good to 1-2 GHzGNDPWRZ01Z01Z02Example 2200 MHz model parasitics of via stubGNDPWRLZ02Z01Z03via up to another signal layerSNG1SNG2Example 3Overall S-parameters can be obtained by the sub-networks using the ABCD or chain scattering matrixes.GNDPWRS02(f)Svia(f)S01(f)ConnectorsPen
13、tium III and Pentium II processor-based NLX motherboard supporting 66-MHz and 100-MHz System BusesVertically(new PCB perpendicular to mb)Horizontal(new PCB parallel to mb)Electrically/Mechanically connect one PCB board or PKG to another.Edge ConnectorsISAISA=Industry Standard Architecture Edge Conne
14、ctorsDIMMDIMM=Dual-Inline-Memory-ModulesEdge ConnectorsPCIPCI=Peripheral Component InterconnectEdge ConnectorsSLOT1APGPGA370PGA(Pin Grid Array)Sockets 2D or 3D field solvers(HFSS)for better modeling Series or mutual inductance have major effects 1st order value can be estimated using empirical formu
15、las Series L slows edge Complicated coupling introducing noise Shunt or mutual capacitance Slows the system edge rate Capacitors sometimes added to reduce impedance discontinuity at connector Connector crosstalk Because of geometry,mutual L has larger effect than mutual C.For first-order estimation,
16、just consider L.Connector“Parasitic”ParametersConnector Effects214ln2432ln2nHpllLnHrllLoo r l r radius of round wire l length p perimeter of rectangular wireApproximation of mutual L between 2 connector pins12ln211ln222nHsllLnHlslsslsllLomom sDIPPLCCQFPBGA CSP；材料方面：金属、陶瓷陶瓷、塑料塑料；引脚形状：长引线直插短引线或无引线贴装球状
17、凸点；装配方式：通孔插装表面组装直接安装Package（封装）（封装）:Chip PackageConnections Made in a Package Attachment of die to package On-package connections Attachment of package to PCBPackage Example:FCBGA Variations of Packagesl Attachment of die to packagep Wirebond Peripheral I/O locationp Flip chip,Area Array I/O locatio
18、nl Attachment of package to PCBp PTH(Pin-Through-Hole),p SMT(Surface Mount Technology)l I/O locationsp Peripheralp Area Arrayl Package Materialsp Plastic,p Ceramicp Thin FilmAttachment of die to packageAttachment of die to packagelA ring of bondwire attach pads on the periphery of the face of the di
19、e.lOn the package,the bondwire lands on package routing.lA bondwire is about 1mil（25.4um）in diameter,50-500mils（1.27mm-12.7mm)long.lA bondwire acts like an inductor.lThe die is placed face down.lSolder balls attach the on-die pads to the surface of the package.lThe die pads are not limited to the pe
20、riphery.lThe technology is self-aligning because the solder ball surface tension pulls the die pads into alignment with the package pads.Wire bondFlip-chipPros and Cons to Wire-Bond and Flip-ChipWire bondFlip-ChipInductanceMuch higher (1-5nH)Much less(.1nH)CrosstalkHigh Virtually none!CostCheap!High
21、MechanicalGoodPhysical tolerances tightsince must align.ThermalBack of die attached to package for max surface area contact and max heat transfer out.Ugly:thermal coefficients of die and package must be similar otherwise expansion will break it.Cooling hard because die lifted off package by solder b
22、alls.Die SizeLimits I/O since pads only around periphery.Die size can be minimized even many I/Os.Wirebond ModelingBall bondBond padChipRouting on PackagePackage dielectric layerPackage Substrate(reference plane in this case)A B C DTo approximate by hand:Subdivide the problem into sections for appro
23、ximation Sections A and D are roughly perpendicular to the plane beneath,so they can be approximated using a simple straight-wire formula.214ln2432ln2pllLrllLooFor round wire,r2 driving chips?CPU 1CPU2ChipsetFull System Modeling Putting Togetherl Multi-drop bus topologies are very common,for example
24、 a chipset with multiple processors.l The effect of packaging on such bus topologies is dependent on the package stub length.Modeling of Small StubsZoZoZbTDstubSmall stub()treated as lumped C:risestubtTD5.0ZoZobstubstubZTDCEffect of Shunt C on RisetimessZZsCZZsC1/)(/)(001001sZsCZZsCT11/)(/)(101001St
25、ep Response:sssVL11121)()(121)(/tUetVtLjs 2/0CZ0022222CZCZtrise.Equivalent risetime:U(t)Z0CZ0Z0Z0Note:(1)Vin=1/2 V(voltage division);(2):U(t)1/s in Laplace Transform domain.Modeling of Long Stubs More VariantsLong stub()modeled as T-line;and Cload modeled as a segment of T-line risestubtTD5.0loadbcC
26、ZTD ZoZoZbTDstubCloadZoZoZbTDstubTDcZbSimplification based on edge rateEffect of Package:Point to point bus topologyEffect of Package:Multi-drop bus topologySmall package stub effect:2)(112)()(2)(/)(/)()(11/)(0000001001001010CjZTCjZCjZCjZZZCjZZCjCjZZCjZZCjcapcapcap002)(2.22.2CZCZtedge22inputedgettts
27、ystem%21 9010TTDstubLong package stub effect:Effect of Package:Multi-drop bus topology%21 9010TTDstubLong package stub effect31752550255025/0002002stubat ZZZZZZss321stubat stubat TVVTV666.0)32(0.1stubat B VVTV 33.1)32(0.122stubat A Effect of Package:Multi-drop bus topologyADS SimulationADS Simulatio
28、n0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVi n,V0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVout,V0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVC i n,V0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVC out,VADS Simulation0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVs
29、t ubi n,VR eadoutm 3R eadoutm 4m 3t i m e=Vst ubi n=666.7m V1.100nsecm 4t i m e=Vst ubi n=1.111 V1.300nsec0.51.01.52.02.53.03.50.04.00.51.00.01.5t i m e,nsecVst ubout,V1.190E-90.667m 1R eadoutm 5m 1t i m e=Vst ubout=666.7m V1.100nsecm 5t i m e=Vst ubout=1.111 V1.400nsec0.51.01.52.02.53.03.50.04.00.2
30、0.40.60.81.01.20.01.4t i m e,nsecVst ub,V780.0p1.333 m 2R eadoutm 6m 2t i m e=Vst ub=1.333 V700.0psecm 6t i m e=Vst ub=888.9m V1.000nsec3213122123232TTZoZoZoZoRsZoZoVinitialVsZoZo0-2VZoRs=ZoVstubRL=ZoVstuboutVstubinBACD0A23T2TA B C D1V1V-1/3V2/3V=0.6667V2/3V2/3V2/3V2/3V=0.6667V4/3V=2(2/3)V =1.333V(2
31、/3)(-1/3)V=-2/9V-2/9V4/3V-4/9V=8/9V=0.8889V4/9V10/9V=1.111V4/9V=(2/3)(2/3)V2/3V+4/9V=10/9V=1.111Vc0DLattice Diagram for Stub Example3l Interconnect is the path that connects one silicon die (e.g.CPU,chipset,memory)to another.p Silicon has driving and receiving buffers.p Vias are vertical metal inter
32、connections that connect different metal layers(within packages and PCB boards and on silicon)p Connectors are designed to connect multiple PCB boardsp Packages have vias and traces designed to interface die and PCB boardsp PCB boards have vias and traces to connect various component packages.Summary
