1、Electroplating Solder Bumping Flip Chip Technology电镀焊球凸点倒装焊技术电镀焊球凸点倒装焊技术Electroplating Solder Bumping Process电镀焊球凸点工艺电镀焊球凸点工艺Process Flow of Electroplating Solder Bump电镀焊球凸点工艺流程 ChipPR openingChipElectroplated solder bumpMushrooming2.Sputter Under Bump Metal金属层溅射金属层溅射3.Coat with PR覆盖光胶覆盖光胶4.Pattern
2、for bump凸点光刻凸点光刻5.Electroplating Cu and Sn/Pb焊料电镀焊料电镀6.Remove Resist去除光胶去除光胶1.Wafer with Al pad钝化和金属化晶片钝化和金属化晶片ChipPassivationAl contact padChipUBMChipThick photoresist filmChip7.Strip Under Bump Metal去除去除UBMChip8.Reflow回流回流 Chipsolder ball after reflowElectroplating Solder Bumping Process电镀凸点制备工艺电镀
3、凸点制备工艺Peripheral array solder bumps 周边分布凸点Area array solder bumps 面分布凸点 The peak temperature of reflow process回流焊峰值温度：220 C.The effective bump pitch for peripheral array周边分布有效凸点间距：125 m.Process Specification工艺参数工艺参数 Photoresist Thickness 光刻胶厚度光刻胶厚度:40100 m Bump Material凸点材料凸点材料:63Sn/37Pb Bump height
4、 凸点高度凸点高度:75140 m UBM layer凸点下金属层凸点下金属层:Ti/W-Cu,Cr-Cu Min.effective pitch of bump 最小有效凸点间距最小有效凸点间距:125 m I/O array输入输入/输出分布输出分布:peripheral array周边分布周边分布 and area array面分布面分布Flip Chip on Low-Cost Substrate SamplesSamples with Different Dimensions PCB上不同尺寸倒装焊样品Flip Chip on Flexible substrate在软质底板上倒装焊D
5、irect chip attach on low-cost PCB,flexible substrate 已完成在低成本PCB和软质底板上倒装焊工艺的研究MCM-L technology 多芯片组装技术.Stencil Printing Bumping Flip Chip Technology丝网印刷凸点倒装焊技术丝网印刷凸点倒装焊技术Electroless UBM and Stencil Printing化学镀UBM和丝网印刷工艺 nThe most potential low cost flip chip bumping method.最具前景的低成本倒装焊凸点制备方法nUsing ele
6、ctroless Ni/Au as UBM system 用化学镀镍/金作为凸点下金属层nmaskless process 无掩膜工艺nCompatible with SMT process 与表面贴装工艺兼容nFlexible for different solder alloys适用于不同焊料合金ChipSolder BumpElectroless Ni/AuPassivationStencil Printing Process Flow丝网印刷工艺流程Process flow of Stencil Printing Process丝网印刷工艺流程(not to scale)Wafer p
7、reparation晶片制备(Passivation and Al pads)Zincation Pretreatment锌化预处理Electroless Ni/Immersion Au化学镀镍/金Stencil Printing丝网印刷Solder Reflow and Cleaning焊料回流和清洗Stencil Printing Process Flow 丝网印刷工艺流程nSketch of process flowElectroless Ni/Au Stud(Cross section)化学镀镍化学镀镍/金金Solder Paste Printing浆料印刷浆料印刷Reflow回流回流
8、Process Specification 工艺参数nI/O pads with a pitch of 400 m are used for testing diceThe limitation of this process is the pitch of 150 m.测试芯片I/O凸点间距：400微米nThickness of Ni/Au UBM is 56m.Ni/Au UBM厚度：56微米nDifferent solder alloys are available.Solder alloys from different vender:Kester,Multicore,Alpha Me
9、tal,Indium,Different composition:eutectic Pb-Sn,lead free可应用不同供应商凸点焊料Samples by Stencil Printing Bumping丝网印刷凸点工艺样品Flip Chip on PCB for Testing在PCB上倒装焊测试样品Reliability Test可靠性测试可靠性测试Reliability Test Design可靠性测试设计可靠性测试设计nJEDEC Standard for Test Design JEDEC标准测试设计(Joint Electron Device Engineering Counc
10、il)Test Dice 测试芯片Reliability Test(Thermal Cycling)可靠性测试Mechanical Properties Test(Bump shear)机械测试Low cost substrate低成本底板Bumping凸点制备Assembly(Bonding and Underfilling)装配工艺Reliability Test Results可靠性测试结果Both Bumping Process Produce Reliable samples两种凸点工艺样品的可靠性两种凸点工艺样品的可靠性Thermal CyclingTemperature&Humi
11、dityHigh temperature StorageMultiple ReflowsNo failure after 1500 cyclesNo degradation after 1000 hours No degradation after 10 reflowsStencil Printing Flip ChipElectroplating Flip ChipPass 1000 cycles-40 C+125 C1cycle/hrJESD22-A104-BNo degradation after 100 hours 120 C and 85%RHNo degradation after
12、 1000 hours150 C,AirJESD22-A103-ANormal Reflow ProfileResultsConditionStandardWafer Level Input/Output Redistribution晶片级输入晶片级输入/输出再分布输出再分布Wafer Level Input/Output Redistribution Applications 晶片级I/O再分布技术的应用nConvert chips designed for perimeter wirebond to area flip chip bonding.可转换已设计芯片，由周边丝键合至面分布倒装焊
13、键合nIncrease I/O density while increase I/O pitch.增加I/O密度同时增加I/O间距nImprove reliability and manufacturing yield.改善可靠性和制造率nAdapt existing chips designed for wirebonding to flip chip.在现有已设计的丝键合芯片上应用倒装焊技术Advantages 优点WL-Input/Output redistribution will eliminate the underfilling process in Flip Chip Tech
14、nology!再分布技术可消除倒装焊技术中填充塑封工艺再分布技术可消除倒装焊技术中填充塑封工艺!Redistribute tight pitch perimeter I/O to loose pitch array bonding and increase package reliability 增加焊点间距和封装可靠性增加焊点间距和封装可靠性PeripheralArea Array Structure of I/O Redistribution 再分布结构5mUBM(Ni)5mBCB_20.5m/5mMetal_2(Ti-W/Cu)5mBCB_1Key Feature:Silicon sub
15、strateBCB2Metal 2UBMAl pad120m80m100m120m250m300mPassivationSolder ballBCB1Critical Dimension:500mSolder ball pitch 300mSolder ball size(diameter)Process Flow of Redistribution Test Chip再分布测试芯片工艺流程再分布测试芯片工艺流程Wafer startMetal1 Al SputteringPhotolithographyWet etchPassivation PE-CVD SiO2Photolithograp
16、hyPlasma dry etchBCB 1Spin coatingPhotolithographyHard CureMetal 2Al sputteringPhotolithographyWet etchBCB 2 Spin coatingPhotolithographyHard CureMetal 2Ti-W/Cu seed sputteringPhotolithographyCopper electroplatingTi-W/Cu seed removeStencil solder printingor Solder Electroplating orSome of Flip Chip
17、Equipment倒装焊设备Electroplating Station电镀台Wafer Stencil Printer晶片丝网印刷机Flip Chip Bonder倒装焊机Possible Business Relationship 合作方式nLicense of the technology 技术许可证nJoint venture with HKUST injecting the technology合资：香港科大注入技术nContract research-pre-defined deliverable for an agreed amount of$.合作研究nOther schemes 开展其它合作模式nFor more information contact 联系人Prof.Philip Chan 陈正豪教授(852)2358-7041Email:eepchanust.hk
