1、FPGA综合设计实例1 键盘扫描与显示 矩阵式键盘:行,列矩阵是键盘以行列形式排列,矩阵是键盘以行列形式排列,键盘上每个按键其实是一个键盘上每个按键其实是一个开关电路,当某键被按下时,开关电路,当某键被按下时,该按键对应的位置就呈现逻该按键对应的位置就呈现逻辑辑0状态状态.行扫描方式:逐行送0电平,读取列的状态,以判断按下的键号.列扫描方式:逐列送0电平,读取行的状态,以判断按下的键号.以行扫描为例以行扫描为例:1给行依次送给行依次送0111,1011,1101,1110信号信号;2读取列电平状态读取列电平状态,数码管显示library ieee;use ieee.std_logic_1164
2、.all;use ieee.std_logic_unsigned.all;entity key_scan is port(column:in std_logic_vector(3 downto 0); -列状态列状态 scan_cnt:in std_logic_vector(3 downto 0);-扫描字扫描字 row:out std_logic_vector(3 downto 0);-行状态行状态 key_pressed:out std_logic);-按键有效与否按键有效与否,后续判断为零则为有键按下后续判断为零则为有键按下end ;architecture rtl of key_sca
3、n isbegin row=1110 when scan_cnt(3 downto 2)=00 else 1101 when scan_cnt(3 downto 2)=01 else 1011 when scan_cnt(3 downto 2)=10 else 0111; key_pressed=column(0) when scan_cnt(1 downto 0)=00 else column(1) when scan_cnt(1 downto 0)=01 else column(2) when scan_cnt(1 downto 0)=“10 else column(3); end rtl
4、 ;按键扫描控制程序按键扫描控制程序按键处理控制模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity scan_count isport(clk:in std_logic;-clockscan_clk:in std_logic;-1khz clkkey_pressed:in std_logic;-检测按键有效与否,停止计数. scan_cnt:out std_logic_vector(3 downto 0);-计数end;arc
5、hitecture behav of scan_count issignal qscan:std_logic_vector(3 downto 0);begin scan_1:process(clk,scan_clk,key_pressed) begin if(clkevent and clk=1)then if(scan_clk=1 and key_pressed=1)then qscan=qscan+1; end if; end if; end process; scan_cnt=qscan; end;按键消抖控制模块按键消抖控制模块 library ieee; use ieee.std_l
6、ogic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity debounce is port(key_pressed:in std_logic; clk:in std_logic;-同步时钟同步时钟 scan_clk:in std_logic;-1khz clock key_valid:out std_logic); end; architecture behav of debounce is begin debounce:process(clk,scan_clk,key_presse
7、d) variable dbnq:std_logic_vector(5 downto 0); begin if(key_pressed=1)then dbnq:=111111;-unkey_pressed,count reset at 63 elsif(clkevent and clk=1)then if scan_clk=1 then if dbnq/=1 then dbnq:=dbnq-1;-key_pressed not enough long time end if; end if; end if; if dbnq=2 then key_valid=1;-key_valid after
8、 key_pressed 1/63k second else key_validbutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_codebutt_code=1111;-fend case;end if; end if;end process;end ; 电锁控制模块电锁控制模块library ieee;use ieee.std_logic_1164.all;use ieee.std_
9、logic_unsigned.all;entity ctrl is port(data_n:in std_logic_vector(3 downto 0); key_valid,clk:in std_logic; enlock:out std_logic; d,c,b,a:out std_logic_vector(3 downto 0);end;architecture aaa of ctrl is signal acc,reg:std_logic_vector(15 downto 0);signal nc:std_logic_vector(2 downto 0);signal qa,qb:s
10、td_logic;beginkeyin:block is begin process(data_n,key_valid) begin if data_n=1101 then acc=0000000000000000; nc=000; elsif key_validevent and key_valid=1 then if data_n1101 then if nc=4 then acc=acc(11 downto 0)&data_n; nc=nc+1; end if;end if;end if;end process;end block; lock:block is begin process
11、(clk,data_n) begin if(clkevent and clk=1)then if nc=4 then if data_n=1110 then reg=acc; qa=1;qb=0; elsif data_n=1111 then if reg=acc then qa=0;qb=1; end if;end if;end if;end if;end process;end block; enlock=qa and not qb; d=acc(15 downto 12); c=acc(11 downto 8); b=acc(7 downto 4); a=acc(3 downto 0);
12、 end aaa;动态扫描显示控制模块动态扫描显示控制模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity sel_display isport(clk:in std_logic; d,c,b,a:in std_logic_vector(3 downto 0); db_out:out std_logic_vector(3 downto 0); dis_out:out std_logic_vector(3 downto 0);en
13、d entity;architecture rtl of sel_display is signal sel:std_logic_vector(1 downto 0); signal dis:std_logic_vector(3 downto 0); signal db:std_logic_vector(3 downto 0);begincounter:block is signal q:std_logic_vector(6 downto 0); begin process(clk) begin if clkevent and clk=1 then q=q+1; end if; end pro
14、cess; sel=q(1 downto 0); end block counter;multiplexer:block is begin process(sel) begin if sel=0 then db=d; dis=0111; elsif sel=1 then db=c; dis=1011; elsif sel=2 then db=b; dis=1101; elsif sel=3 then db=a; dis=1110; end if; end process; end block multiplexer; db_out=db; dis_out=dis; end rtl;实例实例1
15、数字钟设计数字钟设计实时显示时、分、秒实时显示时、分、秒分析:分析:1、最小计时单位:秒。因此,首先要由时钟产生、最小计时单位:秒。因此,首先要由时钟产生1HZ的信号;的信号;2、对秒进行、对秒进行0-59的计数,并且有进位功能,且显示;的计数,并且有进位功能,且显示;3、对分进行、对分进行0-59的计数,并且有进位功能,且显示;的计数,并且有进位功能,且显示;4、对时进行、对时进行0-59的计数,且显示;的计数,且显示;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.allentity second i
16、s port(clk,clr:in std_logic;-clk=1Hz sec1,sec0:out std_logic_vector(3 downto 0); co:out std_logic );end second;architecture arch of second isbegin process(clk,clr) variable cnt1,cnt0:std_logic_vector(3 downto 0); begin if clr=0 then cnt1:=0000; cnt0:=0000; elsif clkevent and clk=1 then if cnt1=0101
17、and cnt0=1000 then co=1; cnt0:=1001; elsif cnt01001 then cnt0:=cnt0+1; else cnt0:=0000; if cnt10101 then cnt1:=cnt1+1;else cnt1:=0000; co=0; end if; end if; end if; sec1=cnt1; sec0 kinside:=0; -停止状态或空挡 when 001= kinside:=28; -第一档,慢速行驶状态,行驶100m需要28个时钟周期 when 010= kinside:=24; -第二档 when 011= kinside:=
18、20; -第三档 when 100= kinside:=16; -第四档 when 101= kinside:=12; -第五档 when 110= kinside:=8; -第六档 when 111= kinside:=4; -第七档,也是速度最大的档 end case; if reset=1then s_state:=s0; elsif clkevent and clk=1then case s_state is when s0= cnt:=0;clkout clkout=0; if stop=1 then s_state:=s0; -相当于无客户上车 elsif sp=000 then
19、s_state:=s1; -有客户上车,但车速位0,即客户刚上车还未起步 elsif cnt=kinside then cnt:=0;clkout=1; s_state:=s1; else cnt:=cnt+1; s_state:=s1; end if; end case; end if; end process;end behav;kilometers模块模块此模块主要用于记录行进的距离。通过对此模块主要用于记录行进的距离。通过对clkout信号的计数,可以计算信号的计数,可以计算行驶的距离行驶的距离kmcount。一个。一个clkout脉冲相当于行进脉冲相当于行进100m,所以只要记,所以
20、只要记录录clkout的脉冲数目即可确定共行进的距离。的脉冲数目即可确定共行进的距离。kmcount1为十分位,为十分位,kmcount2为个位为个位,kmcount3为十位,分别为十进制数。为十位,分别为十进制数。Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity kilometers is Port(clkout,reset:in std_logic; kmcnt1:out std_logic_vector(3 downto 0); kmcnt2:out std_logic_vect
21、or(3 downto 0); kmcnt3:out std_logic_vector(3 downto 0);end kilometers;architecture behav of kilometers isbegin process(clkout,reset) variable km_reg:std_logic_vector(11 downto 0);begin if reset=1then km_reg:=000000000000; elsif clkoutevent and clkout=1then -km_reg(3 downto 0)对应里程十分位 if km_reg(3 dow
22、nto 0)=1001then km_reg:=km_reg+0111; -十分位向个位的进位处理 else km_reg(3 downto 0):=km_reg(3 downto 0)+0001; end if; if km_reg(7 downto 4)=1010then km_reg:=km_reg+01100000; -个位向十位的进位处理 end if;end if;kmcnt1=km_reg(3 downto 0);kmcnt2=km_reg(7 downto 4);kmcnt3 waittime:=0;timecount if sp=000then t_state:=t2; el
23、se waittime:=0;t_state:=t1; end if; when t2 = waittime:=waittime+1; timecount=0; if waittime=1000 then timecount=1; -20s,即1000个clk,产生一个时间计费脉冲 waittime:=0; elsif stop=1then t_state:=t0; elsif sp=000then t_state:=t2; else timecount=000001000000then price=0100; Else price=0011)or(kmcnt3=0001)then enabl
24、e=1; Else enable=0; End if; End process;kmmoney2:process(reset,clkout,clk,enable,price,kmcnt2)variable reg2:std_logic_vector(11 downto 0);variable clkout_cnt:integer range 0 to 10;begin if reset=1 then cash1001 then reg2(7 downto 0):=reg2(7 downto 0)+00000111; if reg2(7 downto 4)1001 then cash =reg2
25、+000001100000; else cash=reg2; end if; else cash00001001then reg2(7 downto 0):=reg2(7 downto 0)+00000110+price; if reg2(7 downto 4)1001then cash=reg2+000001100000; else cash=reg2; end if; else cash=reg2+price; end if; else clkout_cnt:=clkout_cnt+1; end if;end if;end if;end process;count1=cash(3 down
26、to 0); -总费用的个位count2=cash(7 downto 4); -总费用的十位count3=cash(11 downto 8); -总费用的百位End behav;分频模块对系统的时钟进行分频,以模拟轮胎的滚动。 (a)100分频 (b)10分频Library ieee;Use ieee.std_logic_1164.all;entity fp is port(clr,clk:in std_logic; newclk:out std_logic);end fp;architecture behav of fp issignal tem:integer range 0 to 99;
27、begin process(clk,clr) begin if(clr=1)then tem=0; newclk=0; elsif(clkevent and clk=1)then if(tem=99)then tem=0; newclk=1; else tem=tem+1; newclk=0; end if; end if; end process;end behav;Library ieee;Use ieee.std_logic_1164.all;entity fp10 is port(clr,clk:in std_logic; newclk:out std_logic);end fp10;
28、architecture behav of fp10 issignal tem:integer range 0 to 9;begin process(clk,clr) begin if(clr=1)then tem=0; newclk=0; elsif(clkevent and clk=1)then if(tem=9)then tem=0; newclk=1; else tem=tem+1; newclk=0; end if; end if; end process;end behav;显示模块library ieee;use ieee.std_logic_1164.all;entity se
29、v_yima isport(s:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0);end sev_yima;architecture rtl of sev_yima isbegin with s select q= 1000000when 0000, 1111001when 0001, 0100100when 0010, 0110000when 0011, 0011001when 0100, 0010010when 0101, 0000010when 0110, 1111000when 0111, 00000
30、00when 1000, 0010000when 1001, 1111111when others;end rtl;实例实例3 频率计设计频率计设计 要求:对输入信号进行频率的测量并实时要求:对输入信号进行频率的测量并实时显示。显示。 分频器模块分频器模块时钟信号源输出的时钟信号频率高达50MHz,经过分频器将其分频为1Hz、4Hz、500Hz和1000Hz时钟信号。这四种信号再经过1/2分频,得到时间基准信号,其中1000Hz的时钟基准信号用于动态扫描译码电路,1Hz的时钟基准信号用于计数器的始能信号。library ieee;use ieee.std_logic_1164.all; ent
31、ity fenpin is port( clk: in std_logic;-50MHz clk1: out std_logic;-1Hz clk2: out std_logic;-4Hz clk3: out std_logic;-500hz clk4: out std_logic -1khz );end fenpin;architecture arch of fenpin isbeginprocess(clk) variable cnt1: integer range 0 to 49999999; variable cnt2: integer range 0 to 12499999; var
32、iable cnt3: integer range 0 to 99999; variable cnt4: integer range 0 to 49999; variable x1,x2,x3,x4: std_logic:=0;begin if clkevent and clk=1 then if cnt149999999 then cnt1:=cnt1+1; else cnt1:=0; x1:=not x1; end if; if cnt212499999 then cnt2:=cnt2+1; else cnt2:=0; x2:=not x2; end if; if cnt299999 th
33、en cnt3:=cnt3+1; else cnt3:=0; x3:=not x3; end if; if cnt449999 then cnt4:=cnt4+1; else cnt4:=0; x4:=not x4; end if; end if; clk1=x1; clk2=x2; clk3=x3; clk4=x4;end process;end arch; 计数器模块计数器模块计数器模块始能端door输入分频器模块分频出的0.5Hz为基准时钟信号频率。计数器sig输入待测信号与基准时钟信号进行比较,并且计数。q03.0对应的是个位输出,q13.0对应的是十位输出,q23.0对应的是百位输出
34、,q33.0对应的是千位输出。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity measure is port( sig,door: in std_logic; q3,q2,q1,q0,dang: out std_logic_vector(3 downto 0) );end measure;architecture arch of measure is signal c0,c1,c2,c3,c4,c5,c6 : std_logic_vector(3 downto 0):=0000; s
35、ignal suo : std_logic;-lock the count numberbeginprocess(door,sig)beginif sigevent and sig=1 then if door=1 then suo=1; if c01001 then c0=c0+1; else c0=0000; if c11001 then c1=c1+1; else c1=0000; if c21001 then c2=c2+1; else c2=0000; if c31001 then c3=c3+1; else c3=0000; if c41001 then c4=c4+1; else
36、 c4=0000; if c51001 then c5=c5+1; else c5=0000; if c61001 then c6=c6+1; else c6=0000; end if; end if; end if; end if; end if; end if; end if; else -to if door=1 c0=0000;c1=0000;c2=0000;c3=0000; c4=0000;c5=0000;c6=0000;suo=0; if suo=1 then if c6/=0000 then q3=c6;q2=c5;q1=c4;q0=c3;dang=0100; elsif c5/
37、=0000 then q3=c5;q2=c4;q1=c3;q0=c2;dang=0010; elsif c4/=0000 then q3=c4;q2=c3;q1=c2;q0=c1;dang=0010; else q3=c3;q2=c2;q1=c1;q0=c0;dang=0001; end if; else null; end if; end if; -to if door=1 else null; -to if sigevent and sig=1 then end if;end process;end arch;锁存器模块锁存器模块锁存器模块主要由1个锁存器组成,主要作用是锁存计数器的计数值
38、。设置锁存器可以使数据显示稳定可靠,不会由于周期性的清零信号而使数码管不断闪烁。锁存信号由控制电路产生,在1个周期的计数时间结束时,锁存器立即锁存计数值。锁存器的数据输入端与计数器数据输出端连接,数据输出与动态扫描译码电路中的显示译码电路连接,时钟输入端与基准时钟电路端连接。在信号的上升沿,将计数器中的测量数据存入锁存器。a23.0对应的是个位输入,a33.0对应的是十位输入,a43.0对应的是百位输入,a53.0对应的是千位输入,q23.0对应的是个位输出,q33.0对应的是十位输出,q43.0对应的是百位输出,q53.0对应的是千位输出锁存,clk连接的是分频器分频出的1000HZ的信号。
39、 library ieee;use ieee.std_logic_1164.all;entity lock is port( clk: in std_logic; a5,a4,a3,a2,a1,a0: in std_logic_vector(3 downto 0); q5,q4,q3,q2,q1,q0: out std_logic_vector(3 downto 0) );end lock;architecture arch of lock issignal aa5,aa4,aa3,aa2,aa1,aa0: std_logic_vector(3 downto 0);beginprocess(c
40、lk)begin if clkevent and clk=0 then aa5=a5;aa4=a4;aa3=a3;aa2=a2;aa1=a1;aa0=a0; end if; q5=aa5;q4=aa4;q3=aa3;q2=aa2;q1=aa1;q0=aa0;end process;end arch;译码器模块译码器模块译码器模块主要由4个显示模块组成。主要功能是将锁存器保存的4位二进制计数值转换成相应的数码管显示代码,显示模块输出端与4个7段数码管相连,可以在数码管上显示所测频率的十进制输出值。d3.0对应的是译码信号的输入,q6.0对应的是译码信号的输出。 实例实例4 交通灯模拟系统设计交通
41、灯模拟系统设计结合DEII实际,拟用不同颜色发光二极管模拟南北方向和东西方向的红绿灯;每个方向有红、绿、黄三个灯,并能对绿灯放行时间进行设置和调整。控制模块设计控制模块设计 本模块主要实现对两个方向红绿灯的交替显示控制。本模块主要实现对两个方向红绿灯的交替显示控制。 clockholdcountnum5.0numa4.0numb4.0redagreenayellowaredbgreenbyellowbflashcontrollerinst其中其中Clock是时钟源,为分频模块的输出信号;是时钟源,为分频模块的输出信号;hold是控制信号是控制信号 ,起保持功,起保持功能能; countnum是
42、计数模块的输出信号,为一个周期的循环计数值;是计数模块的输出信号,为一个周期的循环计数值;numa是是a组交通灯输出;组交通灯输出;numb是是b组交通灯输出组交通灯输出; reda是是a组红灯输出;组红灯输出;greenda是是a组绿灯输出;组绿灯输出;yellowa是是a组黄灯输出;组黄灯输出;redb是是b组红灯输出;组红灯输出;greendb是是b组组绿灯输出;绿灯输出;yellowb是是a组黄灯输出;组黄灯输出;flash是闪烁输出是闪烁输出 library ieee;use ieee.std_logic_1164.all;entity controller isport(clock
43、:in std_logic; hold: in std_logic; countnum:in integer range 0 to 49; numa,numb:out integer range 0 to 25; reda,greena,yellowa:out std_logic; redb,greenb,yellowb:out std_logic; flash:out std_logic);end controller;architecture arch of controller isbegin process(clock) begin if falling_edge(clock) the
44、n if hold=0 then reda=0; redb=0; greena=1; greenb=1; yellowa=1; yellowb=1; flash=1; else flash=0;- if countnum=19 then numa=20-countnum; reda=1;greena=0; yellowa=1; elsif countnum=24 then numa=25-countnum; reda=1; greena=1; yellowa=0; else numa=50-countnum; reda=0; greena=1; yellowa=1; end if;- if c
45、ountnum=24 then numb=25-countnum; redb=0; greenb=1; yellowb=1; elsif countnum=44 then numb=45-countnum; redb=1; greenb=0; yellowb=1; else numb=50-countnum; redb=1; greenb=1; yellowb=0; end if; end if; end if;end process;end arch;计数模块设计计数模块设计 本模块主要实现一个周期的循环计数,在此以本模块主要实现一个周期的循环计数,在此以50秒为一个周期进行循环计数,秒为一
46、个周期进行循环计数,当然可以根据实际情况进行调整,如调整为当然可以根据实际情况进行调整,如调整为60秒或秒或120秒。秒。0-50的计数范围用二的计数范围用二进制表示则需要六位,因此本模块的计数输出为六位,如果需要调整计数周期,进制表示则需要六位,因此本模块的计数输出为六位,如果需要调整计数周期,则计数的输出位数需要相应调整。则计数的输出位数需要相应调整。clockresetholdcountnum5.0counterinst1library ieee;use ieee.std_logic_1164.all;entity counter isport(clock:in std_logic; r
47、eset:in std_logic; hold: in std_logic; countnum:buffer integer range 0 to 49);end counter;architecture arch of counter isbegin process(reset ,clock) begin if reset=0 then countnum=0; elsif rising_edge(clock) then if hold=0 then countnum=countnum; else if countnum=49 then countnum=0; else countnum=20
48、 then num1=2; num2=10 then num1=1; num2=numin-10; else num1=0; num2 reg_clr cnt3:=cnt3+1; if x=1then if cnt3=27 then-一个编码的长度为一个编码的长度为4a,约,约27个时钟周期个时钟周期 reg_clr=1;state1:=t0; else state1:=t1; end if; else state1:=t0; end if; end case; end if;end process pro1;-进程进程pro2:对红外接收信号解码:对红外接收信号解码pro2:process(
49、clk,reg_clr,state,flag)begin if(reg_clr=1)then state=s0;reg12 cnt1=0;cnt2=0;reg_bell=0; reg12=000000000000; if x=0then state cnt1=4 then state=s2; else state -接收到的信号为接收到的信号为1 cnt2=cnt2+1;reg12=reg12(10 downto 0)&1; if cnt2=11 then state=s4; else state -接收到的信号为接收到的信号为0 cnt2=cnt2+1;reg12=reg12(10 down
50、to 0)&0; if cnt2=11 then state=s4; -是否接收完是否接收完12位编码位编码 else state -已接收到已接收到12位编码,并进行校验处理位编码,并进行校验处理 state=s0; if flag=0 then qreg12=reg12;flag=1; else flag=0; if reg12=qreg12 then z=reg12;state=s0;reg_bell=1; else z cnt1=0; if x=0then state bell cnt4:=cnt4+1; bell reg2=00000001; if control=1 then re