1、2022-5-25VLSI Test: Lecture 71Lecture 7 Fault Simulation 第七讲：故障模拟2022-5-25VLSI Test: Lecture 72Contents内容目录1.Problem and motivation2.Fault simulation algorithms3.Random Fault Sampling4.Summary2022-5-25VLSI Test: Lecture 731 Problem and Motivation问题和驱动lFault simulation Problem: Given A circuit A sequ
2、ence of test vectors A fault modelDetermine Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faultslMotivation Determine test quality and in turn product quality Find undetected fault targets to improve tests2022-5-25VLSI Test: Lecture 741.1 Faul
3、t simulator in a VLSI Design ProcessVLSI设计过程中的故障模拟器Verified designnetlistVerificationinput stimuliFault simulatorTest vectorsModeledfault listTestgeneratorTestcompactorFaultcoverage?Remove tested faultsDeletevectorsAdd vectorsLowAdequateStop2022-5-25VLSI Test: Lecture 751.2 Fault Simulation Scenario
4、故障模拟假定lCircuit model: mixed-levelMostly logic with some switch-level for high-impedance (Z) and bidirectional signalsHigh-level models (memory, etc.) with pin faultslSignal states: logicTwo (0, 1) or three (0, 1, X) states for purely Boolean logic circuitsFour states (0, 1, X, Z) for sequential MOS
5、circuitslTiming:Zero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedback2022-5-25VLSI Test: Lecture 761.2 Fault Simulation Scenario (continued)故障模拟假定（续）lFaults:Mostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faults; analog circui
6、t fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsFault-dropping - a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisFault sampling - a random sample of faults is simulated
7、when the circuit is large2022-5-25VLSI Test: Lecture 772 Fault Simulation Algorithms故障模拟算法lSerial / 串行算法lParallel / 并行算法lDeductive / 演绎算法lConcurrent / 并发算法lDifferential / 差分算法2022-5-25VLSI Test: Lecture 782.1 Serial Algorithm串行算法lAlgorithm: Simulate fault-free circuit and save responses. Repeat foll
8、owing steps for each fault in the fault list:Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectorslAdvantages:Easy to implement; needs only a tr
9、ue-value simulator, less memoryMost faults, including analog faults, can be simulated2022-5-25VLSI Test: Lecture 792.1 Serial Algorithm (Cont.)串行算法（续）lDisadvantage: Much repeated computation; CPU time prohibitive for VLSI circuitslAlternative: Simulate many faults togetherTest vectors Fault-free cir
10、cuit Circuit with fault f1Circuit with fault f2Circuit with fault fnComparatorf1 detected?Comparatorf2 detected?Comparatorfn detected?2022-5-25VLSI Test: Lecture 7102.2 Parallel Fault Simulation并行故障模拟lCompiled-code method; best with two-states (0,1)lExploits inherent bit-parallelism of logic operati
11、ons on computer wordslStorage: one word per line for two-state simulationlMulti-pass simulation: Each pass simulates w-1 new faults, where w is the machine word lengthlSpeed up over serial method w-1lNot suitable for circuits with timing-critical and non-Boolean logic2022-5-25VLSI Test: Lecture 7112
12、.2.1 Parallel Fault Sim. Example并行故障模拟实例a a b b c c d d e e f f g g 1 1 11 1 11 1 11 1 11 0 11 0 11 0 11 0 10 0 00 0 01 0 11 0 1s-a-1s-a-00 0 10 0 1c c s-a-0 detected s-a-0 detectedBit 0: fault-free circuitBit 1: circuit with c s-a-0Bit 2: circuit with f s-a-12022-5-25VLSI Test: Lecture 7122.3 Deduc
13、tive Fault Simulation演绎故障模拟lOne-pass simulationlEach line k contains a list Lk of faults detectable on k lFollowing true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault listslPO fault lists provide detec
14、tion datalLimitations:Set-theoretic rules difficult to derive for non-Boolean gatesGate delays are difficult to use2022-5-25VLSI Test: Lecture 7132.3.1 Deductive Fault Sim. Example演绎故障模拟实例a a b b c c d d e e f f g g 11101a0b0 , c0b0b0 , d0Le = La U Lc U e0 = a0 , b0 , c0 , e0Lg = (Le Lf ) U g0 = a0
15、, c0 , e0 , g0Ub0 , d0 , f1Notation: Lk is fault list for line k kn is s-a-n fault on line k Faults detected bythe input vector2022-5-25VLSI Test: Lecture 7142.4 Concurrent Fault Simulation并发故障模拟lEvent-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in
16、signal states from the fault-free circuit.lA list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any.lAll events of fault-free and all faulty circuits are implicitly simu
17、lated.lFaults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.)lFaster than other methods, but uses most memory.2022-5-25VLSI Test: Lecture 7152.4.1 Conc. Fault Sim. Example并发故障模拟实例a a b b c c d d e e f f g g 111011111011 00101001001101001
18、111110000110000000 10 11 1a0b0c0e0a0b0b0c0e0d0d0g0f1f12022-5-25VLSI Test: Lecture 7163 Fault Sampling故障采样lA randomly selected subset (sample) of faults is simulated.lMeasured coverage in the sample is used to estimate fault coverage in the entire circuit.lAdvantage: Saving in computing resources (CP
19、U time and memory.)lDisadvantage: Limited data on undetected faults.2022-5-25VLSI Test: Lecture 7173.1 Motivation for Sampling故障采样的驱动力lComplexity of fault simulation depends on:Number of gatesNumber of faultsNumber of vectorslComplexity of fault simulation with fault sampling depends on:Number of ga
20、tesNumber of vectors2022-5-25VLSI Test: Lecture 7183.2 Random Sampling Model随机采样模型All faults witha fixed butunknowncoverageDetectedfaultUndetectedfaultRandompickingNp = total number of faults (population size) C = fault coverage (unknown)Ns = sample size Ns Npc = sample coverage (a random variable)2
21、022-5-25VLSI Test: Lecture 7193.3 Probability Density of Sample Coverage采样故障覆盖率的概率密度 (x-C )2 - - 1 2s s 2p (x ) = Prob(x c x +dx ) = - e s (s (2 p) p) 1/21/2p (x )CC +3s sC -3s s1.0 xSample coverage C (1 - C)VarianceVariance, s , s 2 = - NsMean = CSamplingerrors ss sx2022-5-25VLSI Test: Lecture 7203
22、.4 Sampling Error Bounds采样错误限度 C (1 - C ) | x - C | = 3 - 1/2 NsSolving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate:Where Ns is sample size and x is the measured fault coverage in the sample.Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%.
23、 The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample imulation was about 10% of that for all faults. 4.5C 3s s = x - 1 + 0.44 Ns x (1 - x )1/2 Ns 2022-5-25VLSI Test: Lecture 7214 Summary总结lFault simulator is an essen
24、tial tool for test development.lConcurrent fault simulation algorithm offers the best choice.lFor restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5.5.6.)lFor large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.
