1、Spatial Discrete Model for Clustered Defects on Wafer Maps空间统计模型在半导体制造质量研究中空间统计模型在半导体制造质量研究中的的应用应用Personal profile and Lab introduction 王好：博士研究王好：博士研究生生，2010-2014年年就就读读于于天天津津大大学学工工业业工程工程系系，2014年年至至今今就读就读于于清清华华 大学大学工工业业工工程程系。系。导师：王凯导师：王凯波波，博博士士，博士博士生生导导师师，2006年年在在香香港科港科技技大大学学获获得得博博士士学学位位（工（工业业工工程程与与
2、工程管理学工程管理学），），2007年年加加入入清清华华大大学学工工业业工工程程系系，现，现为为教教授授。王王凯凯波波博博士士的主的主要要研研究方究方 向为向为统统计计质质量量控控制以制以及及数数据据分分析析，并，并强强调调融融合合工工程知程知识识与与统统计计方方法解法解决决工工业业实实际际质量质量问问 题。题。Some research topics in our Lab:Robust Parameter Design For Profile ControlProfile Monitoring And DiagnosticsSpatial And Temporal Models For Ca
3、rbon Nanotube Height Variations 3D Print Quality Control:Distortion And ShrinkageSpatial Correlated Defects Model On Wafer Maps(Todays Topic)Introduction of ICs&chipsIntegrated Circuits(ICs):One of the most wildly used electronic components in industrial production and daily life.Chips:1.A realizati
4、on of IC2.Chips are a set of electronic circuits electricallyinterconnected on semiconductor material plates(wafers)to fulfilcomplex electric functions.3.Used as electric components(CPU,RAM)Relationship between Semiconductor wafer and IC chips1.Wafer:Plane piece made by semiconductor materials2.Chip
5、s:Integrated circles“planted on waferwaferchipFigure1.Real wafersFigure 2.Relationship between Semiconductorwafer(left)and IC chip(right)Figure3.Flow diagram for generic IC process sequenceYield study:Vital indicators in semiconductor fieldsHigh production input:Billions of dollars to build a factor
6、yOver two hundred process steps,half a month.Unsatisfactory output:(Above 10%or even all)chips could be unqualified.Quite a lot of materials,time and resources wasted Yield analysis to:(1)Predict the future outcomes.(2)Monitor the process(3)Find the root cause of defectives.(4)Improve revenues of en
7、terprise.5Yield study:Vital indicators in semiconductor fieldsYield:fraction of output and input，usually 3090%on a wafer.According to the sequential yield loss processes：Wafer process yield Y,:percentage of wafers arriving at probing step;Wafer probe yield Y :percentage that getting through the test
8、ing step;Assembly yield Y caused by the assembly process;Final test yield Y:percentage that make through the final electrical test.Yield loss from wafer probe(Y)is the highest in chips manufacturing processes.Real Examples of Wafer probe yield(Program with Samsung Electronics Co.,Ltd.)Wafer probe yi
9、eld Y:percentage that getting through the testing step;Traditional SPC tools:c chart or p chart Ignore chip level yields and only focus on total yields through a wafer(1)Collect yields wafer by wafer.(2)Build control limits(3)Monitoring the process:abnormal alarms.Advantages：(1)Easy for application(
10、2)Provide some basic information about wafer yields Disadvantages:Loss of informationFocus on chip yield and sum up to wafer yield:identical defects rate distributions for each location 1)Poisson model,identical defects rate at each location Probability that any specific chip containing x defects:2)
11、Negative binomial(NB)model3)Lambert(1992)described zero-inflated Poisson(ZIP)regression 1Assumption:(1)There is a random shock leading to Poisson/binomial/NB processes and(2)This random shock occurs independently with probability p.1 Zero-inflated Poisson regression,with an application to defects in
12、 manufacturing,Technometrics,Taylor&Francis,1992,34,1-14(1)Take chips as independent and identical samples(2)If the wafer presents significant spatial patterns:(3)Not really consider each chip locations defects rate;Just assume identical distribution for each chip.Short comes of the previous modelsI
13、ndependent assumptions of traditional statistics violates real production features!In the view of spatial statistics:Characteristics at proximal locations appear to be correlated,either positively or negatively.Literatures Review:How to capture spatial pattern?Answer of Bae et al.(2007)1:By spatial
14、coordinate.GLSp model:a function of the chips polar coordinates.Successfully captured the global trend of defect rates but failed to capture the local clustering:Real defects mapRegressed defects rate1Bae,S.J.;Hwang,J.Y.&Kuo,W.Yield prediction via spatial modeling of clustered defect counts across a
15、 wafer map IIE Transactions,Taylor&Francis,2007,39,1073-1083Proposed modelVision of geographical statistics:Spatial coordinates-Capture macro scale tendency Spatial random error Capture micro scale correlation of the densitys distribution across a wafer map.STAGE 1:Poisson distribution model At the
16、stage 1,we assume the number of defects of the chip on the location has independent Poisson distribution given density .(1)On each location,(2)Each chip has its own defects rate,determined by its location and neighbors;(3)A Poisson process determines the real defects showed on this location.(4)For t
17、otal sites on a wafer map,there are different Poisson process:The expected value of the observed data is linear related to some predictivevariables via inverse link function:a function of the chips polar coordinatesSTAGE 2:Generalized linear function:predictive variables for the Poisson parameterSTA
18、GE 2B:Assignment of Auto-correlationsFigure 7.Neighbors structure of instrinsic GMRF on wafer map,blue lattices are designated as neighborsFull conditions parameterization:Models implementation on real datasetFigure 7.Real wafer map and typical simulated wafer map showing defects pattern and numbers
19、 in each chipFigure 8(a)linear fitted predictors (b)posterior mean of spatial correlation component(c)total fittedTable 1.Moran I statistic under randomization for residuals in two modelsModels implementation on real dataset DATA-2:Defects are randomly scattered onwafer map.DATA-3:Present some ringl
20、ike patterns DATA-4:bottom-right clustered on wafer map.Table 2.DIC values for GLSp-iCAR and GLSp model on RealData and Data-2,3,4Results summary of the simulation experimentsFigure 9.Average DIC values decrease under 500 simulation experiments,compared with GLSp models.Conclusions and remarksAdvant
21、ages:1)Proposed method not limited to a fix datas generation mode,but can be extend as needed.2)Under higher spatial dependency circumstance,the performance is better;3)Under lower spatial dependency circumstance,the performance is not bad;Problems:1)When the volume of data extends,the MCMC methods may meet with some time consuming problem.2)If measurement data is available on the wafer map,it can also be used as a linear predictor.
