1、Chip Package System(CPS)Thermal Integrity Co-AnalysisChip-Package-System Thermal Integrity SolutionIC Simulation for Thermal-aware EM (RedHawk/Totem)3D IC Package SimulationCTASystem Simulation(Icepak)Chip-aware package and system thermal analysisSystem-aware package and chip thermal and Thermal-awa
2、re EM analysisCTMsConvergedPower MapThermal BCTemperature Map2 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Chip&Board Aware Package Level Thermal Analysis JEDEC board is widely used for easy package level analysis when info about system is not ready or explicitChip dataPkg dataSystem dataPkg dataJEDEC
3、 Board InfoORHTC(Heat Transfer Coefficient)3 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Prototyped BCRedhawk-CTAChip Thermal Model(CTM)from RH/TotemLayer stackupPower(T)M5M1CTM content Temp-dependent tile-based power density maps Per layer metal density map Block Power File (separate input)OD and pow
4、er info(Dynamic+Leakage)T1(Dynamic+Leakage)T2(Dynamic+Leakage)T34 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Metal DistributionM8 Specify Package Design and Result DirectoryCPA_FILES 5 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017./design.mcm./adsCTAPACKAGEMODELConfiguration File(GSR)Setting for Thermal
5、 Analysis Must-have OptionTHERMAL_ANALYSIS 1Test Design Example:POP Design DRAM+Die+Interposer/Package+Thermal Board Prescribed temperature of 50C on DRAM CTM power maps on Die(from RH)50 CThermal Board6 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Invoke RedHawk/Totem-CTAPKG layout viewChip Layout7 20
6、17 ANSYS,Inc.August 3,2017ANSYS UGM 2017Geometry UI SetupColor maps2D Layout ViewLayout ManagerThermal SetupTCL WindowColor MapsRun CTAKey Functions for Thermal Analysis8 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017RedHawk TCL window to input TCL commandsLayout Manager for layout editingThermal Setup
7、dialog for all CTA setupColor Contours to Display ResultsDesign Setup through Layout Manager9 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Set thickness,layer type conductive/dielectric material of target design Remove unnecessary layer info Various setting for design optimization through what-if anal
8、ysisSpecify Info for Bump/Ball10 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Change Bump/Ball to practical values Bump/Ball are crucial info related to heat transferationAdd Molding to enclose Package and Die11 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Set Up Package Configuration12 2017 ANSYS,Inc.Au
9、gust 3,2017ANSYS UGM 2017Stackup of DRAM on Die,i.e.,DRAM on top of CHIP1Heat Source Define:CTM,OD,Power Map13 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017For three die components,user needs to specify its CTM model or uniform power individually.If die adopts CTM power model,also specify its flip/Axis
10、/rotation values to match package design and CTM power mapJEDEC Board Setting in RH-CTA14 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Thermal Boundary Condition(BC)Set up15 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Import HTC from IcePak or User-definedUser-defined setup exampleSpecify env temperature
11、;default 20CSpecify Air speed 0;Specify prescribed temperature on top of DRAMHTC Generation from IcePakIcePakPackage Real Design:mcm fileImport CTMHTC Generation16 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Simulation Configurations17 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017All layers modeled expli
12、citlySolid elements for bumps/TIV100um resolution for CTM diesDefault setting for thermalboard(100 x100 x1.57mm,4L)Thermal Analysis Results18 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Package Level Thermal Profile vs.Heat Source19 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Wrong power map can lead t
13、o a wrong temperature resultCTM(Chip Thermal Model)30 x30 Bin-based Power MapPackage Level Thermal Profile vs.HTC Hotspt and thermal profiles are different according to boundary condition and board design info CPS integrated solution is necessary for accuracyWithout HTCHTC based onPrototyped BCHTC f
14、rom IcePak20 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Demo Video21 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Should includesDesign Set up for package level thermal analysisCTM generation and importBoundary condition and Jedec board settingThermal analysis and result showChip-PackageThermal ToolChi
15、p Power Integrity ToolChip-Package-System Thermal-Aware EM FlowBack-annotationEa kTnMTTF AJeBlacks equation for mean-time-to-failure(MTTF)Temp increase causes EM limit decreasePower LibraryTemperatureEM ViolationsWith Temperature EffectChip Thermal ProfileWire TempEM ViolationsUniform TemperatureIC
16、DesignPackage DesignCTMGeneration3D-IC/SoC/AnalogThermal Analysisw/Thermal CouplingCTMModel22 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Self-heat Calculation Flow in RedHawk/TotemRedHawkTotemTech file/LIB/Dev ModelsLEF/DEF/GDSDSPFw/Signal RCOptional:Diel Thermal CoefCTMP/G wire IavgSignal wire IrmsC
17、TM-based Thermal and wire Self-heat calculation w/thermal couplingWire Self-heat ReportInstance Self-heat ReportThermal Profile/Back-annotationPower EM RunSignal EM Run23 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Tile-based temperature profileEM Color MapsRedHawk View Thermal Maps24 2017 ANSYS,Inc.A
18、ugust 3,2017ANSYS UGM 2017 By layer EM color maps By layer temperature profile mapRedhawk Thermal-aware Resistance and EM vs.Package DesignTo attach picture hereResistance Re-calculatedEM percentage re-calculatedWithout Package Info25 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017With Package InfoDemo Video26 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Show EM analysis with thermal effect Compare the comparison data between normal EM and thermal-aware EM感谢聆听感谢聆听
