课件：数字电路第六章课件.ppt

1、组合逻辑电路Chapter Outline Documentation Standards Digital Circuit Timing and Propagation delay Combinational Logic Design Structures:-Decoders-Encoders-Three-State Buffers-Multiplexers-EXCLUSIVE OR Gates and Parity Circuits-Comparators-Adders/Subtractors-Arithmetic Logic Units(ALUs)6.1 Documentation Sta

2、ndard(文档标准)Documentation of a digital system should provide the necessary information for building,testing,operating,and maintaining the system.Specification:Description of Interface and Function (说明书：接口及功能描述)Block Diagram:Systems Major Function Module and their Basic Interconnections (方框图：主要功能模块及其互

3、联 P345图6-1)Schematic Diagram:showing all the components,their types,and all interconnections(原理图（P360图6-17）)Block DiagramSchematic DiagramHierarchichal schematic structureDocumentation Standard(文档标准)Timing Diagram:showing the logic signals as a function of time(定时图（P363图6-19）)Structure Logic Device

4、Description:showing the operation of the structures (结构化逻辑器件描述)Circuit Description:Explains how the circuit works internally.(电路描述：解释电路内部如何工作)“Hierarchical Design”Gate Symbols(门的符号)&11DeMorgan equivalent symbols(等效门符号（摩根定理）)Inverter(反相器反相器)Buffer(缓冲器缓冲器)Which symbol to use?depends on signal names an

5、d active levels.Signal Names and Active Levels(信号名和有效电平)Signal name:a descriptive alphanumeric label for each input/output signal.In real system,well-chosen names convey information to readers Each signal name should have an active-level associated with it.(有效电平)Active High（高电平有效）Active Low（低电平有效）RE

6、ADYREQUESTGOREADY_LREQUEST_LGO_LSignal Name and Active Levels(信号名和有效电平)The signal is asserted when it is in its active level and negated(or deasserted)when its not in its active level.An Inversion Bubble to Indicate an Active-Low Pin(有反相圈的引脚有反相圈的引脚 表示低电平有效表示低电平有效)Active low signal has a suffix of _L

7、 as part of the variable name.Signal Name and Active Levels(信号名和有效电平)ENABLEDOMYTHINGENABLEDOMYTHING AND,OR,and a large-scale logic element have active-high inputs and outputsThe same elements with active-low inputs and outputs Given Logic Function as Occurring inside that symbolic outline.(给定逻辑功能只在符

8、号框的内部发生给定逻辑功能只在符号框的内部发生)Bubble-to-Bubble Logic Design(“圈到圈”的逻辑设计)Purpose:To make it easy to understand the function of the Logic circuit by choosing appropriate logic symbols and signal names including active-level designators.ERRORFAIL_LOVERFLOW_L ERRORFAIL_LOVERFLOW_LBubble-to-Bubble Logic Design(

9、“圈到圈”的逻辑设计)AASELBDATAAASELBADATA_LBDATA_LDATA6.2 Circuit Timing(电路定时)XZYFWPropagation Delay(传播延迟传播延迟)-A Signal Path as the Time that it takes for a Change at the Input to Produce a Change at the Output of the Path(信号通路输入端的变化引起输出端变化所需的时间信号通路输入端的变化引起输出端变化所需的时间)t tpHL pHL and tand tpLH pLH Maybe Differ

10、entMaybe DifferentPropagation DelayTiming Analysis:Worst-Case Delay(定时分析：取最坏情况延迟定时分析：取最坏情况延迟)XZYFWMaximum Delay(最大延迟最大延迟)Typical Delay(典型延迟典型延迟)Minimum Delay(最小延迟最小延迟)080804323232P366 P366 表表6-26-2152022226.2 Circuit Timing(电路定时)Timing Diagram定时图（时序图）定时图（时序图）GOREADYDAT6.2 Circuit Timing(电路定时)Causali

11、ty and Propagation Delay (因果性和传播延迟）因果性和传播延迟）GOREADYDATtDATtDATtRDYtRDYGOREADYDAT6.2 Circuit Timing(电路定时)Timing Diagram定时图（时序图）定时图（时序图）Minimum and Maximum Delay (最小和最大延迟）最小和最大延迟）GOREADYDATtRDYmintRDYmax6.2 Circuit Timing(电路定时)Certain and Uncertain Transitions (确切的和不确切的转换）确切的和不确切的转换）WRITE_LDATAOUTDATA

12、INtOUTmaxtsetuptOUTminCommonly Used MSI Combinational Logic DevicevDecoders(译码器)vEncoders(编码器)vMultiplexers(多路复用器)vParity Circuits(奇偶校验)vComparators(比较器)vAdders(加法器)Decoder and Encoder(译码器和编码器)Multiple-Input,Multiple-Output Logic Circuit(多输入、多输出电路多输入、多输出电路)Enable Inputs(使能输入使能输入)(输入输入编码编码)(输出输出编码编码)

13、Map 映射映射Enable Inputs must be Asserted to perform Normal Mapping Function(使能输入有效才能使能输入有效才能实现正常映射功能实现正常映射功能)Input Code WordOutput Code WordDecoderDecoder（译码器（译码器）Normally Output Code has More bits than its Input Code (一般来说，输出编码比输入编码位数多一般来说，输出编码比输入编码位数多)EncoderEncoder（编码器（编码器）Output Code has Fewer bit

14、s than its Input Code called an Encoder(输出编码比输入编码位数少，则常称为编码器输出编码比输入编码位数少，则常称为编码器)Decoder and Encoder(译码器和编码器)Most Commonly Used Case使能使能输入输入编码编码输出输出编码编码Map 映射映射DecoderDecoder（译码器（译码器）EncoderEncoder（编码器（编码器）N-Bit Binary Code(n位二进制码位二进制码)2n 中取中取1码码使能使能输入输入编码编码输出输出编码编码Map 映射映射2n中取中取1码码n位二进制码位二进制码(1-out

15、-of 2n)6.4 Decoder（译码器）Binary Decoder (二进制译码器)1.2-to-4 Decoder2-to-4DecoderY0Y1Y2Y3I0I1EN 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0(2-4(2-4二进制译码器真值表二进制译码器真值表 )Truth Table for a 2-to-4 Binary DecoderY0=EN (I1 I2)Y1=EN (I1 I2)Y2=EN (I1 I2)Y3

16、=EN (I1 I2)Yi=EN miDecoder（译码器）0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0InputsEN I1 I2Outputs Y3 Y2 Y1 Y0(2-4(2-4二进制译码器真值表二进制译码器真值表 )Truth Table for a 2-to-4 Binary Decoder2-to-4 DecoderThe 74x139 Dual 2-to-4 Decoder(双2-4译码器74x139)1 X X 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 1

17、 0 1 0 1 0 1 1 0 1 1 0 1 1 1InputsG B AOutputs Y3_L Y2_L Y1_L Y0_LTruth Table for One-half of a 74x139Dual 2-to-4 Decoder74x1391Y01Y11Y21Y31G1A1B2Y02Y12Y22Y32G2A2B1 2 315 14 1345671211109 Logic Symbols for Large-Scale ElementY0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139Y0Y1Y2Y3GAB1/2 74x139G_LABY0_LY1_

18、LY2_LY3_L0 0 0 0 0 0 0 10 0 0 0 0 0 1 00 0 0 0 0 1 0 00 0 0 0 1 0 0 00 0 0 1 0 0 0 00 0 1 0 0 0 0 00 1 0 0 0 0 0 01 0 0 0 0 0 0 03-to-8DecoderI2I1I0Y0Y1Y7Yi=EN mi1 1 1 1 1 1 1 01 1 1 1 1 1 0 11 1 1 1 1 0 1 11 1 1 1 0 1 1 11 1 1 0 1 1 1 11 1 0 1 1 1 1 11 0 1 1 1 1 1 10 1 1 1 1 1 1 1Decoder（译码器（译码器）0

19、0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8(3-8二进制译码器真值表二进制译码器真值表)Truth Table for a 3-to-8 Binary Decoder2.3-to-8 DecoderThe 74x138 3-to-8 Decoder(3-8译码器74x138)低位低位高位高位Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENG1G2A_LG2B_LENEN=G1 G2A G2B =G1 G2A_L G2B_L Yi=EN miYi_L=Yi=(EN mi)ABCG1G2AG2

20、BY0Y1Y2Y3Y4Y5Y6Y774x138EnableY6_L=(CBA)=m6Logic diagram for the 74x138用用7474x138x138设计设计4-16译码器译码器Cascading Binary Decoders N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L思路：思路：16 16个输出需要个输出需要 片片7474x138x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2 任何时刻只有任何时刻只有一片在工作。一片在工作。4 4个输入中，个输入中，哪些位控制片选哪些位控制片选哪些位控制输入哪些位控制输入Conside

21、r:How to make a 5-to-32 Decoder with 3-to-8 Decoder?3232个输出需要多少片个输出需要多少片7474x138x138？控制任何时刻只有一片工作控制任何时刻只有一片工作 利用使能端利用使能端5 5个输入的低个输入的低3 3位控制输入位控制输入5 5个输入的高个输入的高2 2位控制片选位控制片选 利用利用 2 2-4 译码器译码器P391 图图6-37Use decoder and Gates to realize logic functionF=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)Binary decoder：Yi

22、=EN mi Enable inputs are asserted:Yi=mi Yi_L=Yi=mi=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138Use decoder and Gates to realize logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)当使能端有效时当使能端有效时Yi=miUse decoder and Gates to realize logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(

23、X,Y,Z)(0,3,6,7)=M1 M2 M4 M5=m1 m2 m4 m5F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFBCD Decoder(二十进制译码器)Inputs:4-bit BCD codeOutputs:1-out-of 10 CodeY0Y9I0I1I2I3多余的多余的6 6个状态如何处理？个状态如何处理？输出均无效：拒绝输出均无效：拒绝“翻译翻译”作为任意项处理作为任意项处理 电路内部结构简单电路内部结构简单二二-十十进进制制译译码码器器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1

24、0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 1 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 1 1 11 1 1 1 1 0 1 1 1 11 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 11 1 1 1 1 1

25、 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1I3 I2 I1 I00123456789Y0_L Y9_L伪伪码码Dont careSeven-Segment Decoders(七段显示译码器)abcdefgdpNormally use ：Light-Emitting Diodes（LED,半导体数码管半导体数码管）Liquid-Crystal Display（LCD,液晶数码管液晶数码管）LED显示器件显示器件LCD显示器件显示器件LEDabcdefg dp公共阴极公共阴

26、极abcdefg dp公共阳极公共阳极gfedcbadp点阵型显示器点阵型显示器笔划段型显示器笔划段型显示器Seven-Segment Decoders Input code:4-bit BCD 输入信号：BCD码（用A3A2A1A0表示）Output Code:Seven-Segment Code输出：七段码（的驱动信号）a g 1-On，0-Offabcdefg111111011011010011111gfedcba151413121110987654321074LS48显示字型与输入的对应关系显示字型与输入的对应关系0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 0

27、0 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 11 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 11 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 10 0 1 1 1 1 11 1 1 0 0 0 01 1 1 1 1 1 11 1 1 0 0 1 10 0 0 1 1 0 10 0 1 1 0 0 10 1 0 0 0 1 11 0 0 1 0 1 10 0 0 1 1 1 10 0 0 0 0 0 0A3 A2 A1 A0a b

28、c d e f g0123456789101112131415A3A2A1A000 01 11 10000111101001100011000111a七段显示译码器的真值表Ya=A3A2A1A0+A3A1+A2A0Yb=A3A1+A2A1A0+A2A1A0Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图)Yc=A3A2+A2A1A0Yd=A2A1A0+A2A1A0+A2A1A0Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图)Karnaugh Maps f

29、or BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图七段显示译码器的卡诺图)Ye=A2A1+A0Yf=A3A2A0+A1A0+A2A1Karnaugh Maps for BCD-Seven-Segment Decoder(BCD-七段显示译码器的卡诺图七段显示译码器的卡诺图)Yg=A3A2A1+A2A1A0BIN/7SEGabcd efgA3A2A1A0BI/RBO RBILT74x48Design BCD-Seven-Segment Decoder 逻辑抽象，得到真值表 输入信号：BCD码（A3A2A1A0）输出：七段码（的驱动信号）a g 1 表示亮，0

30、 表示灭 选择器件类型 采用基本门电路实现，利用卡诺图化简 采用二进制译码器实现，变换为标准和形式 电路处理，得到电路图abcdefg6.5 Encoder（编码器）Binary EncoderA0A1A2I0I1I71 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1 2nInputsnOutputsI0 I1

31、I2 I3 I4 I5 I6 I7 A2 A1 A0(3(3位二进制编码器的真值表位二进制编码器的真值表)Truth Table for a 8-to-3 EncoderGuarantee:-one and only one input will be asserted at a time(任何时刻只有一个任何时刻只有一个输入端有效。输入端有效。)1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0

32、10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0(3(3位二进制编码器的真值表位二进制编码器的真值表)Encoder（编码器）Truth Table for a 8-to-3 Encoderthis is the exact opposite of a decoderA0=I1+I3+I5+I7A1=I2+I3+I6+I7A2=I4+I5+I6+I7How to deal with multiple requests?-more than One Inputs are assertedPrio

33、rityPriority（优先级（优先级）1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0(3(3位二进制编码器的真值表位二进制编码器的真值表)Encoder（编码器）Truth Table for a 8-to-3 EncoderA2A1A0ID

34、LEI7I6I5I4I3I2I1I0 In order to write logic equations for the priority encoders outputs we first define eight intermediate variables H0-H7Highest-Priority(数大优先数大优先)Priority Encoder(优先编码器优先编码器)H7=I7H6=I6 I7H5=I5 I6 I7H0=I0 I1 I2 I6 I7A2A1A0IDLEI7I6I5I4I3I2I1I0 In order to write logic equations for the

35、 priority encoders outputs we first define eight intermediate variables H0-H7Highest-Priority(数大优先数大优先)Priority Encoder(优先编码器优先编码器)A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7 The IDLE Output is asserted if No Inputs are asserted.IDLE=I0 I1 I6 I7输输入入输输出出EI_L有效有效没有输入请求没有输入请求EO_L有效有效Enable Input有输入请求有输入

36、请求EI_L有效有效GS_L有效有效A2A1A0EI74x148I7I6I5I4I3I2I1I0GSEO54321131211106791415使能输出，用于级联使能输出，用于级联 EO选通输出选通输出GSThe 74x148 Priority EncoderA2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2个个74x148级联为级联为16-4优先编码器优先编码器 输入：由864，需8片74x148 每片优先级不同（怎样实现？）保证高位无输入时，次高位才工作 高位芯片的EO端接次高位芯片的EI端用用8-3优先编码器优先编码器

37、74x148级联为级联为64-6优先编码器优先编码器A2A1A0GSEOEII7I0片间优先级的编码片间优先级的编码 利用第利用第9 9片片7474x148x148 每片的每片的GSGS端接到第端接到第9 9片的输入端片的输入端 第第9 9片的输出作为高片的输出作为高3 3位（位（RA5RA5RA3RA3）片内优先级片内优先级片间优先级片间优先级 输出：输出：6 6位位低低3 3位位高高3 3位位8 8片输出片输出A2A2A0A0通过或门作为通过或门作为最终输出的低最终输出的低3 3位位RA2RA2RA0RA0分析判定优先级电路：（利用分析判定优先级电路：（利用7474x148x148 ）8个

38、个_电平有效输入电平有效输入I0_LI7_L，_的优先级最高的优先级最高 地址输出地址输出A2A0，_电平有效电平有效 若输出若输出AVALID高电平有效，则表示高电平有效，则表示_A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0AVALID低低I0_L至少有一个输入有效至少有一个输入有效高高P514 题题6.53设计优先级电路：设计优先级电路：（利用（利用7474x148x148 ）8个输入个输入I0I7高电平有效，高电平有效，I7优先级最高优先级最高 地址输出地址输出A2A0，高电平有效高电平有效 如果没有输入有效，输出如果没有输入有效，输出IDLE有效有效I7I0

39、A2A1A0IDLEA2A1A0GSEOEII7I074x148P514 题题6.526.6 Three-State Devices(三态器件)Three-State Buffer(Three-State Driver)三态缓冲器（三态驱动器）Three States:Active High(1)，Active Low(0),Hi-Z Various three-state buffersThree-State Devices Three-State Device allow Multiple Sources to Share a Single“Party Line”As long as On

40、ly One device“talk”on the Line at a time （三态器件允许多个信号源共享单个（三态器件允许多个信号源共享单个“同线同线”，条件是每条件是每次只有一个器件工作）次只有一个器件工作）(Figure 6-52)Typical Three-State Devices are Designed So that they go into the Hi-Z state Faster than they come out of the Hi-Z state.（对典型的三态器件，进入高阻态比离开高阻态的时间快）（对典型的三态器件，进入高阻态比离开高阻态的时间快）ABCG1G

41、2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2fighting（冲突（冲突）利用使能端进行时序控制利用使能端进行时序控制三态器件允许信号共享单个三态器件允许信号共享单个“同线同线”（party line）典型的三态器件，进入高阻态比离开高阻态快典型的三态器件，进入高阻态比离开高阻态快P0P1P7SDATAEN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC2:001237SDATAP0P1P2P3P7Dead Time(截止时间截止时间)Standard SSI an

42、d MSI Three-State Buffer (标准SSI和MSI三态缓冲器)The 74x541 Octal three-state bufferA1A2A3A4A5A6A7A8G1G2Y1Y2Y3Y4Y5Y6Y7Y874x541A1A8G1G2Y1Y874x541DB0:7A1A8G1G2Y1Y874x541Notation of Data Bus Notation of Data Bus（数据总线的表示法）（数据总线的表示法）A1B1DIRTransfer Data in Either Directions By Transfer Data in Either Directions

43、By Using Three-State TransceiverUsing Three-State Transceiver(利用三态缓冲器实现数据双向传送利用三态缓冲器实现数据双向传送)Bus Transceiver(总线收发总线收发)DIRG_L6.7 Multiplexer（多路复用器）Digital Switch,Multi-Switch,Data Selector (又称数据开关、多路开关、数据选择器)（缩写：MUX）Under Select Controlling Signals,Select One of the Multi-Inputs to the Output (在选择控制信

44、号的作用下，从多个输入数据中选择其中一个作为输出。)MultiplexerENSELD0Dn-1YEnable 使能使能Select 选择选择n个个1位数据源位数据源数据输出（数据输出（1位）位）10niiiDmENYENSELD0Dn-1YEnable(使能使能)Select(选择选择)N Data Sources(n个个b位数据源位数据源)Data Output(数据输出数据输出)（b位）位）EN_L C B A Y Y_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3

45、 D3D4 D4D5 D5D6 D6D7 D7(8输入输入1位多路复用器位多路复用器)Truth Table for a 74x1518-Input,1-bit MultiplexerENABCD0D1D2D3D4D5D6D7YY74x15143211514131211109756EN_L C B A Y Y_L1 X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 1 0 1D0 D0D1 D1D2 D2D3 D3D4 D4D5 D5D6 D6D7 D7(8输入输入1位多路复用器位多路复用器)Truth Table for

46、a 74x1518-Input,1-bit MultiplexerHow to get a logic equation for a MUX output?10niiDmENYi01234567Y=(EN_L)(CBA D+CBA D+CBA D+CBA D+CBA D+CBA D+CBA D+CBA D)输入输入G_L S1 X0 00 1 0 0 0 01A 2A 3A 4A1B 2B 3B 4B(2输入输入4位多路复用器位多路复用器)Truth Table for a 74x157输出输出1Y 2Y 3Y 4Y2-Input,4-bit MultiplexerGS1A1B2A2B3A3B

47、4A4B1Y2Y3Y4Y74x157235611101413115479121G_L 2G_L B A 1Y 2Y1 1 X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 1 0 01C0 2C01C1 2C11C2 2C21C3 2C31C0 01C1 01C2 01C3 0 0 2C0 0 2C1 0 2C2 0 2C3(4输入输入2位多路复用器位多路复用器74x153真值表真值表)4-Input,2-bit MultiplexerTruth Table for a 7

48、4x153 AB1C01C11C21C31Y74x15365431421G17101112132C02C12C22C32G152Y9双双4 4选选1 1Expanding Multiplexers(扩展多路复用器)Expanding Bit(扩展位)How to Realize 8-Input,16-bit Multiplexer?From 8-Input,1-bit to 8-Input,16-bit (由8输入1位8输入16位)Need 16 74x151,Each Chip Process 1-bit (需要16片74x151，每片处理输入输出中的1位)Expanding Multipl

49、exers(扩展多路复用器)Expanding Bit(扩展位)Select-Inputs Connect to C,B,A of Each Chip(选择端连接到每片的C,B,A)Note:The Fanout Ability of Select field(注意：选择端的扇出能力)（驱动16个负载）ENYYABCD0D7Expanding Multiplexers(扩展多路复用器)Expanding Inputs(扩展数据输入端的数目)How to realize 32-Input,1-bit Multiplexer (如何实现32输入，1位多路复用器？)Inputs from 8 to

50、32,Need 4 chips(数据输入由832，需4片)How to control Select Inputs -By High bit plus Low bit.(如何控制选择输入端？分为：高位低位)ENYYABCD0D7Expanding Multiplexers(扩展多路复用器)Expanding Inputs(扩展数据输入端的数目)如何实现32输入，1位多路复用器？High Bits plus Decoder as Select (高位译码器进行片选)Low Bits Connect to C,B,A of each Chip (低位接到每片的C,B,A)Output Using