1、 6.Designing with PLD 6.1 Programmable logic devices 6.2 Combinational circuit PLDs 6.3 Sequential circuit PLDs6.4 PLD programming tools6.5 Using read-only memories1 6.1 Programmable logic devices1.Internal structure of PLDsProgrammable logic devices contain gates and flip-flops so that the intercon
2、nection between the components can be altered to implement various logic functions.Combinational logic PLDs that containing only basic logic gates are usually organized as an array of AND gates and OR gates that implement sum-of-product expressions.Sequential logic PLDs add flip-flops to the outputs
3、.Whatever logic arrangement,a general requirement of a PLD is to have a means of changing the interconnections to form a different logic configuration.2 6.1 Programmable logic devices2.Development of PLDsThe original method was to manufacture the devices with semiconductor fuses.Initially they are i
4、ntact within the device which provides extensive interconnections.Selected fuses are then blown by the user to obtain the desired interconnections using special PLD programmer.Once a fuse is blown,the connection cannot be remade.Therefore,they are not re-programmable.Now,programmable PLDs are availa
5、ble which use semiconductor erasable read-only memory technology.3 6.1 Programmable logic devicesThe connections depend upon stored binary information.A memory cell exists at each connection point to store a 0 to maintain a connection or a 1 to disable a connection.Semiconductor memory-based PLDs pr
6、ovide the capability to alter the interconnections rapidly and many times.Manufacturers also produce PLDs with permanent connections.To achieve the fixed connections,specific integrated circuit masks must be created.4 6.2 Combinational circuit PLDs1.Programmable logic arrays PLAsThe interconnection
7、structure for a combinational circuit PLD is a two-dimensional array with programmable connections at the crossover points.5 6.2 Combinational circuit PLDsSimplified field programmable logic array diagramA PLA with 16 inputs and 8 independent outputs6 6.2 Combinational circuit PLDsEach output can pr
8、oduce a sum-of-product expression consisting of up to 48 product terms,and each product term can have up to 16 input variables or their inverse.The number of product terms is determined by the number of AND gates,and the number of variables in each product term is determined by the number of inputs
9、to the circuit.The crossover connections are done with a semiconductor fuse in series with a diode to form the input of a gate.7 6.2 Combinational circuit PLDsThere are four conditions for each input variables.(a)Un-programmed state:Both the true and inverse variables connections are left intact.(b)
10、True variable selected:The true variable is selected by removing the inverse connection.8 6.2 Combinational circuit PLDs(c)Inverse variable selected:The inverse variable is selected by removing the true connection.(d)No variable selected:Both connections are removed.9 6.2 Combinational circuit PLDsE
11、xp1:Using a PLA to generate the function f1=ABC,f2=AB+BCThe Xs indicate the connections are left intact.PLA has both programmable connections to the inputs to the AND gates and programmable connections to the inputs to the OR gates.10 6.2 Combinational circuit PLDs2.Programmable array logic PALPAL h
12、as only programmable connections to the inputs of the AND gates.In a PAL,each AND gate is directly wired to one input of one OR gate.Typically,eight AND gates will be connected to the inputs of each OR gate.PAL16L8 is an example of a combinational circuit PAL.11PAL16L812 6.2 Combinational circuit PL
13、DsThere is a maximum of 16 inputs and 8 outputs,some outputs are shared with inputs.PAL16L8The outputs are provided with three-state buffers which can be enabled by a product function of the inputs and feedback variables.The shared input/output connections can be used as inputs when the outputs are
14、disabled.13 6.2 Combinational circuit PLDsThe devices that either active-low or active-high outputs can be programmed by incorporating a programmable true/inverse are called generic array logic devices(GAL).The programming connection left intact will create a true output,removing the programmable co
15、nnection will create an inverse output.True/inverse output circuit14 6.3 Sequential circuit PLDs1.Registered PLDsIn registered PLDs,flip-flops are integrated into the device.All the outputs are clocked by a single clock signal.Synchronous sequential circuit using PLA/PAL15 6.3 Sequential circuit PLD
16、s2.MacrocellsMacrocells are repeated circuits inside a PLD with selectable functions.An example of a macrocell which can select either a flip-flop output or a path around it is shown.Example macrocell with buried flip-flops16 6.3 Sequential circuit PLDsThe flip-flop that is physically further from i
17、ts output pin and integrated into the macrocell is called buried flip-flop.Example macrocell with buried flip-flopsTwo multiplexers are controlled by the programmable connections.When it is left intact,the input 0 is selected.When it is removed,the input 1 is selected.17 6.4 PLD programming tools1.P
18、LD programmingPLD programming is to identify which connections should be removed according to the specification given in the form of Boolean expression,truth table or state transition diagram,which is normally done by software.The output of the software includes a file holding the required connectio
19、n patterns(programming map).It is then used to drive PLD programmer.Some software also includes a logic simulator to verify the logic correctness of the design before programming the PLDs.18 6.4 PLD programming tools2.ABEL source file structurePrograms can be written in ABEL language to specify the
20、logic function to be implemented by the PLD.Statements can specify the device to be used and the names can be allocated to the pins.The output functions are typically described by Boolean expressions.19 6.4 PLD programming toolsBasic ABEL source structuremodule module_nametitle Name to be printed in
21、 filedevice_id device device_type;identifiers pin pin_numbers;equationstest_vectorend module_nameABEL source fileHeaderDeclarationLogic descriptionsTest vectorsEnd 20 6.4 PLD programming tools The optional test vector defines collection of input values and expected output values,which is used with t
22、he ABEL simulator to establish whether the design is logically correct.The logic description consists of a list of Boolean expressions defining outputs in terms of the inputs.The ABEL compiler takes the source file and creates the necessary documentation and connection patterns to be downloaded to p
23、rogram the PLD.21 6.5 Using read-only memories1.Read-only memoriesRead-only memory(ROM)is a type of memory whose contents are normally only accessed for reading but not accessed for writing.Non-volatile:the information is not lost when the power is removed.Primary use:to hold information that must b
24、e present when the computer system is switched on.22 6.5 Using read-only memories2.Structure of read-only memoriesThe basic structure of a read-only memory consists of a two-dimensional array of memory cells,each cell storing the value of one binary digit as shown below.Each cell has unique position
25、 in the array given by a row and a column address.23 6.5 Using read-only memories3.Types of read-only memories Fixed ROMThe stored information can never change after manufacture.Programmable ROM (PROM)Erasable PROM (EPROM)There are several types of ROMs whose information can be altered by erasing th
26、e stored information and writing new information into the cells.They are:24 6.5 Using read-only memories4.Read the stored informationA row address is provided to select all the cells on the row.A column is selected with a column address to finally select the memory cell.Select the required memory ce
27、ll Read the stored informationThe stored information passes from the cell down the column to a single output pin.25 6.5 Using read-only memories5.Implement combinational logic functionsAs the output values depend upon the contents of the memory cells selected by the inputs.Hence,the memory can be used to implement combinational logic functions.Exp2:Suppose the combinational function given is to be implemented in a read-only memory.26 6.5 Using read-only memoriesTruth table of function for ROM implementation27
