SoC设计与验证课件.ppt

1、SoC设计与验证实验一 RTL设计1本课程的学习内容nSoC设计方法：基于IP的方法nSoC的设计实现（自顶向下）：软件实现，硬件实现（逻辑仿真、逻辑综合、物理设计）n物理设计：由于时间的关系，作为选做内容n下面的内容，结合项目设计实验进一步学习和实践基于IP的设计方法和自顶向下的设计实现方法2Turbo Eagle SoCn体系结构nIP模块nCPUnDSPn外围接口n存储器nBUSn软件3第三讲 内容nRTL级设计nTE的RTL设计4RTL设计nRegister Transition Level寄存器传输级设计是一种硬件结构形式nRTL设计中数据来自寄存器，计算完成后的结果存入寄存器，即设

2、计以寄存器为边界构建n寄存器：多位的时序逻辑（触发器和锁存器），用于存储电路状态5RTL：行为和结构混合设计HDLLogic SynthesisFloorplanningPlacementRoutingTape-outCircuit ExtractionPre-Layout SimulationPost-Layout SimulationDesign Capture6RTL设计有限状态机n设计以寄存器为边界构建COMBINA T I O N ALLOGICRegiste r sOutputsNext st a t eCLKQDCurrent S t a teInputs7RTL设计流水线结构R

3、EGREGREGlogaCLKCLKCLKOutbREGREGREGlogaCLKCLKCLKREGCLKREGCLKOutbReferencePipelined8时序逻辑：registerqLatch电平敏感 DClkQDClkQnFlip Flop时钟沿敏感ClkClkDDQQ9基于锁存器和触发器的设计n在一个时钟周期内，组合逻辑完成一次计算，把计算结果存到时序逻辑中NLatchLogic1Logic2PLatchfFFsLOGICtp,combf10RTL级设计设计输入n利用硬件描述语言可以对RTL级的设计进行设计输入nVerilog中一般利用过程结构（initial，always），引

4、入寄存器，构建RTL级设计n逻辑综合器可以对RTL级HDL进行优化实现11RTL级设计逻辑综合n逻辑综合器可以将RTL级的HDL转换为寄存器和组合逻辑结构，并映射到具体的工艺库n逻辑综合器是自顶向下设计流程中最关键的EDA工具之一12自顶向下的设计方法n逻辑综合器使得自顶向下的设计方法成为可能nASIC和SoC的设计方法取代全定制方法，成为数字VLSI的主流方法nASIC是基于标准单元的方法，而SoC是基于IP的方法13第三讲 内容nRTL级设计nTE的RTL设计14实验目的n掌握基于IP集成的SoC的设计方法n进一步熟悉和掌握利用cadence工具进行自顶向下的设计实现的过程n完成IP集成、

5、逻辑仿真以及逻辑综合过程15实验内容n在现有的Turbo Eagle设计的基础上，增加一个IP软核PCI bridge，实现系统对外部PCB板上的PCI总线接口的支持nRTL设计：增加PCI软核n软件设计：增加PCI软核需要的软件，并编译实现n逻辑仿真：PCI单元仿真和全系统仿真n设计实现：对新的TE进行逻辑综合和物理设计16时间安排（第二周第八周）n第二周第三周：IP集成方法（包括PCI IP核的RTL设计）n第四周第五周：包括PCI IP的Turbo Eagle的逻辑仿真n第六周第七周：逻辑综合和门级仿真n第八周：项目检查17实验要求n设计内容：完成软核的集成、软件设计和实现、逻辑仿真和逻

6、辑综合的内容，物理设计为选做内容n设计报告：提交设计报告n考察方式：设计数据和设计报告各占据期末成绩的50n参考文件：570/starter_kit/slides/下的文件18实验：第一部分nPCI软核的逻辑设计与集成nPCI总线IPnRTL设计n软件设计19PCI软核的逻辑设计与集成nPCI软核nThe PCI-Bridge HDL code软核的RTL描述文件nA full standalone testbench ready for simulationnExample C firmware for the Leon to program the PCI-Bridgen提供给我们软核（在

7、starter kit目录下），我们要利用软核实现IP集成，包括硬件集成和软件实现n并对集成后的系统进行验证和实现20项目设计：RTL设计nPCI总线的工作原理nPCI总线IP的结构nPCI总线IP的仿真验证nIP集成n软件实现（不作要求）21PCI总线的工作原理n参考”PCI local bus specification”nPCI总线的specn总线的信号n总线的工作22The PCI BusnPCI Special Interest Group:nDeveloped in 1993 for Intel Personal ComputersnPCB板上的总线，在PC中连接各种外围设备23T

8、he PCI Bus：SpecificationsnSynchronous 33 MHz transfers,33MHz x 4byte=132Mb/secn32 Multiplexed Address/Data Lines(saves pins and cost)nBasic Transfers:1)Address Phase,2)Data PhasenCPU Architecture independent(also used by Sun,Apple etc.)nSupports Plug&Play with Configuration Registers/Cycles24The PCI

9、 Bus：SpecificationsnBus Master:“PCI Initiator”,Bus Slave:“PCI Target”nBurst Data Phases continue until Initiator deasserts Frame#n66MHz,64 bit Versions availablenSupports 5V and 3.3V operationnBus Signal Integrity guaranteed with special PCI-IO pads(slew limited)nOnly 4 Slots allowed,Extensions only

10、 with PCI-to-PCI Bridge25PCI总线的工作原理n参考”PCI local bus specification”nPCI总线的specn总线的信号n总线的工作26PCI 总线信号nSystem SignalsnClk:33MHz or 66Mhz,Data synchronized to rising edgenRST#:Asynchronous Reset,asserted for 100usec27PCI 总线信号nData SignalsnAD31:0nMultiplexed 32-bit Address/Data BusnAddress Phase:Followi

11、ng High-Low transistion on“Frame#”nData Phase:IRDY#and TRDY#must be low to complete transfernBurst transfer:Data Phase lasts several cycles,Frame#goes High in last cyclenC/BE#3:0nAddress Phase:Indicates the type of transfernData Phase:Indicates which bytes are valid(Byte-Enable)nPar:Used to implemen

12、t Even Parity28PCI总线信号：Control SignalsnFrame#:Indicate Address/Data Phase,End of TransfernIRDY#:Initiator ReadynTRDY#:Target ReadynStop#:Used by Target to cancel/suspend a transfernLock#:For Initiator to get exlusive access to a TargetnDEVSEL#:Target indication that it was selectednIDSEL:Unique for

13、each slot,indicates Configuration CyclenPCI Initiator Arbitration SignalsnREQ#:Unique for each slot,Requests the BusnGNT#:Unique for each slot,Grants the BusnSlot-unique signals:System Arbiter can choose arbitration algorithm29PCI总线的工作原理n参考”PCI local bus specification”nPCI总线的specn总线的信号n总线的工作30PCI Co

14、nfiguration CyclesnPCI Supports Plug&Play，插上PCI器件以后，系统启动过程中会自动检查，并为该器件分配地址空间nPCI Bridge作为amba总线上的一个器件，有固定的地址，在本设计中将占据DES的地址nPCI Bridge需要为PCB板上挂在PCI总线上的器件分配地址n为了支持即插即用，PCI总线协议中包括配置周期，来让host对PCI器件进行地址分配31PCI Configuration Cyclesn在配置周期中，PCI总线对总线上的器件进行配置，即根据需要分配地址n这不同于一般的IO和存储器的寻址方式，一般来说，总线上的器件都被给定一段地址，

15、就像PCI Bridge在amba总线上一样nPCI-Bridge负责启动PCI总线的配置周期n配置周期也分为读写操作，host从器件读取器件名称和ID等信息，并把基址base address写到器件中的寄存器中，根据器件的需要分配其一段地址空间32PCI Configuration CyclesnHow to address a device before it has an address?nThe PCI Configuration Read and Write CyclesnEach slot has an IDSEL linenThat line is asserted,and AD

16、0:1 is 00nAD7:2 provides the address of the configuration registernC/BE3:0 specifies“Configuration Read”or“Configuration Write”33PCI总线的工作时序n从地址周期开始，然后进入数据周期n数据传输期间FRAME信号有效nIRDY和TRDY都有效期间传输数据nDEVSEL信号通知总线，该目标器件正在被读写34项目设计：RTL设计nPCI总线的工作原理nPCI总线IP（pci_bridge）的结构nPCI总线IP的仿真验证nIP集成n软件实现（不作要求）35The Goal

17、:Bring in the PCI BusPCI BridgeWishboneSlaveWishboneMasterPCIInitiatorPCITargetPCIArbiterPCITargetAmbaWishboneWrapperAmba BusTurbo EagleTestbenchnThe PCI-Bridge has 2-directional data flownFrom the PCI Bus to the PCI-Target to the Wishbone MasternFrom the Amba Bus to the Wishbone Slave to the PCI In

18、itiatornFor this project we only use the outbound directionnReceived PCI data is stored in“PCI_OUTPUT”,compare to Golden FilePCI_OUTPUT PCI Bus36PCI总线器件寻址的实现nBridge采用image的方法来实现对PCI器件的寻址和配置n对于wishbone slave方式来说，bridge中包括最多5个image来表示可能的PCI器件n来自amba（wishbone）总线的地址被映射到某个image上，经过地址转换寻址该image所表示的PCI总线上的

19、器件37PCI-Bridge OperationnThe PCI-Bridge can have up to 5 ImagesnImage 0 is mandatory,provides Register accessnThis project uses Image 0 and Image 1nImage 1 is configured at run-timeAmba BusImage 0Image 1Image 2Image 3Image 4Bus Address=Image 1-4:Address TranslationPCI BusImage 0:AccessPCI-BridgeRegi

20、stersMatchesany Image?PCI-Bridge38The Imaging MechanismnImage translation is necessarynThe PCI side memory map is known only at runtimenCannot hope that the Amba memory map matches the PCI sidenEach Implemented Image has 4 RegistersnBase AddressnAddress MasknTranslation RegisternControl Register39Th

21、e Imaging MechanismnEach Implemented Image has 4 RegistersnFor every imcoming address on the Amba busnChecks if it fits the Base address of Image1 through Image4nChecks the control register if translation is enablednIf yes,bits specified in Mask are replaced by those in TranslationnThis is the addre

22、ss that is output to the PCI Bus40Translation in the Turbo-EaglenThe PCI-Bridge replaces an other block on the AMBA busnMemory address range:$A012 0000$A013 FFFF 41Translation in the Turbo-EaglenAt the minimum 2 Images are needednImage 0:To access the internal PCI-Bridge RegistersnThis is the only i

23、mage with a hardcoded Base addressnBecause this address does not change even at runtimenFor the Turbo Eagle:Choose$A012 0000nImage 1:To access the PCI-BusnBase Address set to A013 0000 nNo address translationnImage 1 is programed by the Leon in the Firmware42Guest or Host ImplementationnFor every br

24、idge there are 2 fundamental modes1.The main CPU sits on the Amba side2.The main CPU sits on the PCI sidenTherefore,there are 2 implementation modes1.“Host”(acts as a Bus Master on behalf of the Amba-bus CPU)2.“Guest”(acts as a Slave to the CPU on the PCI Bus)43Guest or Host Implementation1.“Host”(a

25、cts as a Bus Master on behalf of the Amba-bus CPU)2.“Guest”(acts as a Slave to the CPU on the PCI Bus)nBiggest difference:Access to the PCI-Bridge internal registers1.“Host”:From the Amba bus,which is where the main CPU is2.“Guest”:From the PCU,which is where the main CPU isnFor the Turbo-Eagle:Sele

26、ct“Host”implementation44The PCI-Bridge RTL Coden在starter_kit/pci_bridge/rtl目录下nNo RTL code modifications necessarynTo verify the Image 0 Base Address:pci_user_constants.v Line 218nTo add more Images(Image 2,3 and 4)pci_user_constants.v Lines 201-204nTo verify that we are doing a“Host”implementationp

27、ci_user_constants.v Line 130nToplevel Module“pci_bridge32”in pci_bridge32.v45The PCI-Bridge RTL CodenToplevel Module“pci_bridge32”in pci_bridge32.vnThere is also a“top.v”nNot used,not needednIllustrates how to place the toplevel module into a padframenBut uses“bufif”statements instead of real pads46

28、项目设计：RTL设计nPCI软核的介绍nPCI总线IP的结构nPCI总线IP的仿真验证nIP集成n软件实现47设计过程n开始进行IP集成之前，先验证一下提供的IP软核的功能是否正确n利用提供的testbench单独对IP进行逻辑仿真n在pci_bridge目录中进行IP的仿真验证n仿真的命令写成了shell脚本文件run_pcin命令中启动仿真器nTestbench和RTL设计 在compile.f文件中指示路径48Running the SimulationnTo run the standalone simulationcd starter_kit/pci_bridgerun_pcidif

29、f PCI_OUTPUT PCI_OUTPUT.goldnThe script“run_pci”both compiles and simulates the RTLnNo output from the“diff”command:“Simulation successful”49The PCI-Bridge TestbenchnThe testbench simulatesnA Wishbone MasternA PCI bus,complete with Arbiter and TargetnNothing is connected to the PCI-Bridge Wishbone M

30、aster PortnThe testbench toplevel is in./testbench/system.vnData is sent from the Wishbone side through the PCI Bridge to the PCI TargetnAll received data is written to PCI_OUTPUTpci_brige32.vDUT“pci_bridge32”pci_side.vSimulates aPCI Arbiter andPCI Target Devicewb_side.vSimulates aWishbone MasterPCI

31、_OUTPUTWishbone SlaveWishbone MasterPCI50Running the SimulationnThe script“run_pci”both compiles and simulates the RTLnThe Big PicturenThe code of“pci_side.v”will be part of the Turbo-Eagle testbenchnThe functionality of“wb_side.v”will go into Leon Firmwaren“pci_bridge32”will be instantiated in the

32、Turbo-Eagle corenThe Wishbone side1.Initializes the registers and Image 1 in the PCI Bridge2.Initializes the PCI Target with a Configuration Write3.Sends the jpeg data that later the Leon will also send4.This means the Golden File here is the same as for the final simulation51Sequence of Testbench E

33、ventsnThe simulation is controlled by“wb_side.v”nThe starting point is the“initial”at line 79nThere are 2 main tasks1.init_PCI_BridgeConfigure the PCI-Target in the PCI-BridgeBrowse the PCI Bus for PCI DevicesInitialize control registers in the PCI-BridgeInitialize Image-1 in the PCI-BridgeInitializ

34、e the PCI-Target device on the PCI-Bus2.send_jpeg_dataSends 146 words of data to the PCI-Target deviceThis is the same data as will be sent later by the Leon52项目设计：RTL设计nPCI软核的介绍nPCI总线的工作原理nPCI总线IP的仿真验证nIP集成n软件实现（不作要求）53IP集成的过程1.Add RTL source code2.Compile RTL source code3.Modify Turbo Eagle core a

35、nd toplevel4.Add Firmware source code5.Compile firmware6.Add Testbench code7.Run RTL Simulation54IP集成：RTL设计过程n如何开始IP集成n利用提供的PCI Bridge RTL 代码n在TE顶层结构中例化该IP，并进行连接n在padframe文件中为该IP增加相应的IO padn利用逻辑仿真器对完成的新的TE系统进行编译，发现错误并改正55RTL设计：第一步n我们已经对提供的pci bridge IP进行了独立验证，下面我们就要把这个IP集成到TE系统中来n该IP是Verilog描述，Creat

36、e a folder$TURBO/srcX2/vlog/pcin然后Copy the PCI-Bridge code and the Amba-Wishbone wrapper theren下面在该目录下进行IP集成56RTL设计：第二步n需要实现的是黄色框内的内容，例化的过程可以参考其他IP的集成方法，如USB模块，也是通过ambaWbWrapper连接到amba总线的PCI BridgeWishboneSlaveWishboneMasterPCIInitiatorPCITargetPCIArbiterPCITargetAmbaWishboneWrapperAmba BusAmba_pci.

37、vTestbenchPCI_OUTPUT PCI Bus57RTL设计：第二步n在pci目录中建立一个verilog文件：amba_pci.v，用来例化pci_bridge和ambaWbWrapper两个模块n顶层模块为amba_pci，其端口需要连接到amba总线和pci总线PCI BridgeWishboneSlaveWishboneMasterPCIInitiatorPCITargetAmbaWishboneWrapperAmba Bus PCI Bus58RTL设计：第二步n顶层模块amba_pci：n其中amba总线的端口为rsr_n和clk以及ahbSlaveIn和ahbSlave

38、Out两组slave接口信号n这些信号同amba_usb.v中相同PCI BridgeWishboneSlaveWishboneMasterPCIInitiatorPCITargetAmbaWishboneWrapperAmba Bus PCI Bus59RTL设计：第二步n顶层模块为amba_pci：n而pci总线接口的信号如图所示，只需要左半部分，即必须的信号即可n具体的信号在pci_bridge32.v中n其中双向IO口的信号需要使用双向IO单元，即TOP目录下的PCI66DGZ单元PCI BridgeWishboneSlaveWishboneMasterPCIInitiatorPCIT

39、argetAmbaWishboneWrapperAmba Bus PCI Bus60PCI IO signals and PCI PadsnMost PCI-Signals are bi-directionalnCore has 3 wires for each signal:input,output and output_enablenConnected to have a bi-directional IO Pad cellnPCI Signal Integrity:nStrict slew rate specificationsnStrict input capacitance spec

40、ificationsnPCI-IO Pad requirementsnBidirectional,with slew limitationnProvided by GSCLib_IO library:PCI66DGZpci_ad_oe_opci_ad_opci_ad_iCoreIO PadcellPCI66DGZPC BoardBonding Pad61双向IO端口的连接n双向IO端口既可以作为输入又可以作为输出端口使用，因此节约了端口数目n该IO单元在使能信号EN的控制下分别把来自电路core的信号由A输出到PAD上，或者把PAD上来的信号通过Y端输入到core中62双向IO端口的连接n例如

41、amba_pci上的双向端口PAR，需要由3个信号连接到双向IO单元n分别取名为PAR_2core,PAR_2pad,PAR_EN_nn在后面的顶层设计中分别连接到双向IO单元的A，Y和EN端63RTL设计：第三步n在pci目录中建立一个verilog文件：amba_pci.v，用来例化pci_bridge和ambaWbWrapper两个模块nPCI IP中包括构成FIFO的存储器模块，仿真过程中使用仿真模型，在pci_bridge/RAM目录下的RAM2P_256x4_fun.vnPut the RAM macro into$TURBO/srcX2/vlog/RAM64TE设计文件：硬件ns

42、rcX2目录TE的硬件代码nRtllib是仿真时用来存放库文件的，没有设计文件n由于本设计中的IP来源不同，有的是VHDL描述，有的是Verilog描述，有的是二者都有nVhdl目录中是VHDL格式的IP，以及系统的顶层描述n而verilog目录中是verilog格式的IP65第四步 RTL代码的编译n对集成后的pci模块进行编译n发现错误并改正nCreate a“pci”folder in$TURBO/design/srcX2/rtllibnThat is where the compiled database will be storednAdd the“pci”entry to$TURB

43、O/design/srcX2/cds.libnThat way the tools will know where to find the database66第四步 RTL代码的编译n参照其他的shell脚本命令的形式nCreate a“compile_pci”in$TURBO/exenAdd“compile_pci”to“compile_all_”nCompile the Turbo Eagle to verifynthat the PCI-Bridge compiles okaynthat the overall code has not been broken67第五步 修改TE顶层代

44、码n完成对PCI IP的修改后，需要修改TE顶层代码，在系统中例化该IP，实现IP集成n顶层为VHDL描述，在TOP目录，其中主要文件有：nTrail_Asic.vhd:顶层文件，为整个设计的最顶层，其中例化了trial_core.vhd和trail_padring.vhd两个文件中的模块nTrail_core.vhd:包括KS_core.vhd和KS_iologic.vhd中的模块ntrail_padring.vhd:包含所有的IO单元nKS_core.vhd:包含所有IP的结构nConfig:对系统中不同entity进行architecture配置nPCI66DGZ.vhd,PDO08CD

45、G.vhd,PDUDGZ.vhd分别为padring中的双向，输出和输入IO单元68第五步 修改TE顶层代码n在KS_core.vhd中原来DES模块的位置例化新IPnCan use Amba-Bus channel#9 for the PCI-Bridgen在KS_core.vhd中例化amba_pci结构n在trail_core.vhd中更新KS_core结构n在trail_padring.vhd中为amba_pci增加IOn更新trail_asic.vhd中的端口和模块n在config文件中，为amba_pci结构配置verilogn并在vhdl/pci/amba_pci.vhd中定义entity amba_pci，可以参考usb结构69第六步 编译修改后的系统代码n利用compile_all命令，对修改后的系统代码进行编译，改正错误n然后在编译，直到没有语法和结构错误，编译通过，准备以后的仿真验证70第三讲 总结nRTL设计基础nTE的RTL设计nPCI总线IPnPCI的集成71