1、1Advanced Packaging Tech2Outline Package Development Trend 3D Package WLCSP&Flip Chip Package3Package Development Trend4 SO Family QFP Family BGA FamilyPackage Development Trend5 CSP Family Memory Card SiP ModulePackage Development Trend63D Package3D Package73D Package IntroductionetCSP StackFunctio
2、nal IntegrationHighLowTape-SCSP(or LGA)S-CSP(or LGA)S-PBGAS-M2CSPStacked-SiP2 Chip StackWirebond2 Chip StackFlip Chip&WirebondMulti ChipStackPackage onPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP 3 S-CSPS-etCSPetCSP+S-CSP PS-fcCSP+SCSP PoP with interposerFS-CSP2FS-CSP1Paper ThinP
3、S-vfBGA+SCSPPiP 5SCSPSS-SCSP(paste)Ultra thin StackD2D3D4D2D2D3D4D2 PoP QFN4SS-SCSP8Stacked DieTop dieBottom dieFOW materilWire9TSV TSV(Through Silicon Via)A through-silicon via(TSV)is a vertical electrical connection(via)passing completely through a silicon wafer or die.TSV technology is important
4、in creating 3D packages and 3D integrated circuits.A 3D package(System in Package,Chip Stack MCM,etc.)contains two or more chips(integrated circuits)stacked vertically so that they occupy less space.In most 3D packages,the stacked chips are wired together along their edges.This edge wiring slightly
5、increases the length and width of the package and usually requires an extra“interposer”layer between the chips.In some new 3D packages,through-silicon via replace edge wiring by creating vertical connections through the body of the chips.The resulting package has no added length or thickness.Wire Bo
6、nding Stacked DieTSV10 Whats PoP?PoP is Package on Package Top and bottom packages are tested separately by device manufacturer or subcon.PoP11PoPPS-vfBGAPS-etCSPLow Loop WirePin Gate MoldPackage StackingWafer Thinning PoP Core Technology12PoP Allows for warpage reduction by utilizing fully-molded s
7、tructure More compatible with substrate thickness reduction Provides fine pitch top package interface with thru mold via Improved board level reliability Larger die size/package size ratio Compatible with flip chip,wire bond,or stacked die configurations Cost effective compared to alternative next g
8、eneration solutions Amkors TMV PoP Top viewBottom viewThrough Mold Via13PoP Ball Placement on top surface Ball Placement on bottom Die Bond Mold(Under Full optional)Laser drilling Singulation Final Visual InspectionBase MtlThermal effect Process Flow of TMV PoP14 Digital(Btm die)+Analog(Middle die)+
9、Memory(Top pkg)Potable Digital Gadget Cellular Phone,Digital Still Camera,Potable Game UnitMemory dieAnalog dieDigital diespacerEpoxyPiP15Easy system integrationFlexible memory configuration100%memory KGDThinner package than POPHigh IO interconnection than POPSmall footprint in CSP formatIt has stan
10、dardball size and pitchConstructed with:Film Adhesive die attach Epoxy paste for Top PKG Au wire bonding for interconnection Mold encapsulation Why PiP?PiP16Material for High Reliability Based on Low WarpageWafer ThinningFine Process Control Top Package Attach Die Attach etcOptimized Package DesignF
11、lip ChipUnder-fillTop epoxyISM PiP Core TechnologyPiP17Memory PKGSubstrateFlip chipMemory PKGFlip chipInner PKGAnalogAnalogSpacerDigitalInner PKGWB PIPFC PIPPiP PiP W/B PiP and FC PiP18WLCSP&Flip Chip Package19WLCSP What is WLCSP?WLCSP(Wafer Level Chip Scale Packaging),is not same as traditional pac
12、kaging method(dicing packaging testing,package size is at least 20%increased compared to die size).WLCSP is packaging and testing on wafer base,and dicing later.So the package size is exactly same as bare die size.WLCSP can make ultra small package size,and high electrical performance because of the
13、 short interconnection.20WLCSP Why WLCSP?Smallest package size:WLCSP have the smallest package size against die size.So it has widely use in mobile devices.High electrical performance:because of the short and thick trace routing in RDL,it gives high SI and reduced IR drop.High thermal performance:si
14、nce there is no plastic or ceramic molding cap,heat from die can easily spread out.Low cost:no need substrate,only one time testing.WLCSPs disadvantageBecause of the die size and pin pitch limitation,IO quantity is limited(usually less than 50pins).Because of the RDL,stagger IO is not allowed for WL
15、CSP.21RDL RDL:Redistribution Layer A redistribution layer(RDL)is a set of traces built up on a wafers active surface to re-route the bond pads.This is done to increase the spacing between each interconnection(bump).22WLCSP Process Flow of WLCSP23WLCSP Process Flow of WLCSP24Flip Chip PackageFCBGA(Pa
16、ssive Integrated Flip Chip BGA)(PI)-EHS-FCBGA(Passive Integrated Exposed Heat Sink Flip Chip BGA)(PI)-EHS2-FCBGA(Passive Integrated Exposed 2 pieces of Heat Sink Flip Chip BGA)MCM-FCBGA(Multi-Chip-Module FCBGA)PI-EHS-MP-FCBGA(Passive Integrated Exposed Heat Sink Multi Package Flip Chip)25Bump26Bump
17、Development27Bump Development28Bump Development29C4 Flip Chip Whats C4 Flip Chip?C4 is:Controlled Collapsed Chip Connection Chip is connected to substrate by RDL and Bump Bump material type:solder,gold30C4 Flip Chip BGA Main Features Ball Pitch:0.4mm-1.27mm Package size:up to 55mmx55mm Substrate lay
18、er:4-16 Layers Ball Count:up to 2912 Target Market:CPU、FPGA、Processor、Chipset、Memory、Router、Switches、and DSP etc.Main Benefits Reduced Signal Inductance Reduced Power/Ground Inductance Higher Signal Density Die Shrink&Reduced Package Footprint High Speed and High thermal support31C2 Flip Chip Whats C2 Flip Chip?C2 is:Chip Connection Chip is connected to substrate by copper post Bump material type:copper post with solder platingSilicon DieCopper postSolder32C2 Flip Chip Process Flow of C233C2 Flip Chip Comparison:C2 Vs C4In some cases,C2 can replace C4 or wire bonding package.34
