1、TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.ATPG Introduction for IP Team TMFreescale
2、Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri
3、-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential an
4、d Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock Di
5、vidersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential and Proprietary Information.Fre
6、escale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Design Verification,Testing and DiagnosisDesign Verification:Be sure the design perform its specified behavior.B
7、efore silicon.Testing:Exercise the system and analyze the response to ascertain whether it behaves correctly.After silicon.Diagnosis:To locate the cause of misbehavior after the incorrect behavior is detected.After silicon.before siliconafter siliconproductionengineeringTMFreescale Semiconductor Con
8、fidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Whats DFTDFT(Design For Test)Testability is a design attribute that mea
9、sures how easy it is to create a program to comprehensively test a manufactured designs quality.Traditionally,design and test processes were kept separate,with test considered only at the end of the design cycle.But in contemporary design flows,test merges with design much earlier in the process,cre
10、ating what is called a design-for-test(DFT)process flow.Testable circuitry is both controllable and observable.In a testable design;setting specific values on the primary inputs results in values on the primary outputs which indicate whether or not the internal circuitry works properly.To ensure max
11、imum design testability,designers must employ special DFT techniques at specific stages in the development process.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are
12、the property of their respective owners.Freescale Semiconductor,Inc.2006.Whats Structured DFT?Structured DFT Provides systematic and automatic approach to enhancing design testability.Goal is to increase the controllability and observability of a circuit.Methods:scan design technique,which modifies
13、the internal sequential circuitry of the design.Built-in Self-Test(BIST)method,which inserts a devices testing function within the device itself.boundary scan,which increases board testability by adding circuitry to a chip.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale
14、and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Whats ATPGATPG(Automatic Test Pattern Generation)Test patterns(test vectors),are sets of 1s and 0s placed on primary in
15、put pins during the manufacturing test process to determine if the chip is functioning properly.ATE(Automatic Test Equipment)determines if the circuit is free from manufacturing defects by comparing the fault-free outputwhich is also contained in the test patternwith the actual output measured by th
16、e ATE.Goal:create a set of patterns that achieves a given test coverage.Then run it on Tester.Pass indicated no related defects exist in this chip.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All oth
17、er product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStru
18、ctured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names a
19、re the property of their respective owners.Freescale Semiconductor,Inc.2006.SCAN Cell/SCAN ChainScan Cell In normal operation(sc_en=0),system data passes through the multiplexer to the D input of the flip-flop,and then to the output Q.In scan mode(sc_en=1),scan input data(sc_in)passes to the flip-fl
20、op,and then to the scan output(sc_out).Scan ChainA set of serially linked scan cells.Each scan chain contains an external input pin and an external output pin that provide access to the scan cells.The scan chain length(N)is the number of scan cells within the scan chain.TMFreescale Semiconductor Con
21、fidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.SCAN ProcedureThe operating procedure of the scan circuitry is as follo
22、ws:1.Enable the scan operation to allow shifting(to initialize scan cells).2.After loading the scan cells,hold the scan clocks off and then apply stimulus to the primary inputs.3.Measure the outputs.4.Pulse the clock to capture new values into scan cells.5.Enable the scan operation to unload and mea
23、sure the captured values while simultaneously loading in new values via the shifting procedure(as in step 1).Before ScanAfter ScanTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or ser
24、vice names are the property of their respective owners.Freescale Semiconductor,Inc.2006.SCAN Waveformscan_clkscan_seLoadshift shift shiftLoad/Unloadshift shift shiftcapturecaptureLoad/UnloadcaptureLoad/UnloadcaptureUnloadTMFreescale Semiconductor Confidential and Proprietary Information.Freescale an
25、d the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.SCAN TypesFull ScanHighly automated process.Highly-effective,predictable method.Ease of use.Assured quality.Partial ScanR
26、educed impact on area.Reduced impact on timing.More flexibility between overhead and fault coverage.Re-use of non-scan macros.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service
27、 names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Stuck-At Fault ModelExample:Single Stuck-At Faults for AND GateThe single stuck-at model is the most common fault model used in fault simulation,because of its effectiveness in finding many common defect types.The st
28、uck-at fault models the behavior that occurs if the terminals of a gate are stuck at either a high(stuckat-1)or low(stuck-at-0)voltage.The fault sites for this fault model include the pins of primitive instances.All s-a-0 faults in the AND gate are equivalents-a-1 s-a-0s-a-1s-a-0s-a-1 s-a-0s-a-0s-a-
29、0s-a-1s-a-1s-a-0s-a-1Possible Errors:6Possible Errors:4TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconduc
30、tor,Inc.2006.Stuck-At Coverage Report#DT -Test Coverage=#FU-#UU-#TI-#BL-#RE#DT -Fault Coverage=#FU Statistics report-#faults#faultsfault class (coll.)(total)-FU(full)1171003 1824936-UC(uncontrolled)32 84UO(unobserved)946 1286DS(det_simulation)3580 8011DI(det_implication)4 10 (protected)1138170 17678
31、04PU(posdet_untestable)784 1806PT(posdet_testable)34 42UU(unused)3035 5344TI(tied)2093 2201BL(blocked)331 333RE(redundant)8272 10462AU(atpg_untestable)13722 27553-test_coverage 98.66%98.30%fault_coverage 97.50%97.31%atpg_effectiveness 99.91%99.92%-Protected Faults alone:test_coverage 98.35%97.85%fau
32、lt_coverage 97.20%96.87%-#test_patterns 271#simulated_patterns 271CPU_time(secs)18364.6-TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respe
33、ctive owners.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan p
34、rocedureScan waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semico
35、nductor,Inc.2006.Combinational Loop&Tri-state ButCombinational LoopNotice that the A=1,B=0,C=1 state causes unknown(oscillatory)behavior,which poses a testability problem.It should be avoid if possible.Tri-state Bus ContentionTri-state Bus is not permitted inside chip.TMFreescale Semiconductor Confi
36、dential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Divided ClockSome designs contain uncontrollable clock circuitry;that is,
37、internally-generated signals that can clock,set,or reset flip-flops.If these signals remain uncontrollable,they could disturb sequential elements during scan shifting.Thus,the system cannot convert these elements to scan.new_clk=scan_mode?tst_clk:gen_clkTMFreescale Semiconductor Confidential and Pro
38、prietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.Async ResetTest Logic Added to Control Asynchronous Resetuse ipt_async_se to control the
39、 mux.new_rst=ipt_se_async_xxx?ext_rst:int_rstTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.20
40、06.Async Reset(2)For the case where both set and reset of a flop are internally generated,either set or reset shall be disabled during scan mode using ipt_mode_scan signal,while other can be muxed with hardreset using ipt_se_async signal.Selection of disabling set/reset signal shall be decided havin
41、g less combinational logic for getting better test coverage.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semic
42、onductor,Inc.2006.Clock GatingClock GatingWhen clk is pulsed from low to high,the latch is disabled and remains so as long as the clk signal stays high.Therefore,even if the output of dff1 changes from high to low as a result of the leading edge of the pulse,that value change cannot propagate throug
43、h the latch and effect clk_en until clk goes low again,enabling the latch.Equally important,scan chains must operate correctly.You can force se to 1 in the load_unload procedure;however,it must be done before any“apply shift”statement.The se signal must be controllable to 1 from the chips primary in
44、puts(IC pins).In IP DFT guide this se signal is connected to ipt_se_gatedclkp.TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owne
45、rs.Freescale Semiconductor,Inc.2006.Clock Gating(2)Clock Gating CellCPE+TEQDQTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owner
46、s.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debugSoft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureSca
47、n waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc
48、.2006.DFT SignalsDFT signalsIpt_mode_scan_xxxIpt_se_xxxIpt_se_async_xxxIpt_se_gatedclkn/p_xxxIpt_si/so_xxxIpt_dbg_tck_xxxIpt_dbg_trst_xxxIpt_dbg_tms_xxxIpt_dbf_tdi_xxxIpt_dbg_tdo_xxxPlease refer to Section 2.3 of TMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Fr
49、eescale logo are trademarks of Freescale Semiconductor,Inc.All other product or service names are the property of their respective owners.Freescale Semiconductor,Inc.2006.AgendaDFT RulesCombinational LoopAsynchronous ResetTri-state Bus ContentionClock DividersClock GatingDFT signalsFor ScanFor debug
50、Soft IP tasks and deliverablesScripts and DemosQ&AWhats it?DFTStructured DFTATPGTerminology in ScanScan cell Scan chainScan procedureScan waveformScan typeScan fault modelScan CoverageTMFreescale Semiconductor Confidential and Proprietary Information.Freescale and the Freescale logo are trademarks o
