1、SpectreVerilog混合信号仿真混合信号仿真共27页1几家几家EDA软件软件公司公司l1、Cadencel2、Synopsys（收购Avanti）l3、Mentor Graphicsl4、Silvacol5、SpringSoft共27页2SPICE仿真器仿真器 lSPICE:a general-purpose analog circuit simulator developed by the University of California,Berkeley.It is used for nonlinear DC,nonlinear transient,and linear AC an
2、alysis.lHspice:a general-purpose circuit simulator from Avanti.It has an extensive set of built-in device models,including models for small geometry MOSFETs and MESFETs.The program is compatible with SPICE input formats.Cadence supports a library of primitives and a full interface for Hspice.lSpectr
3、e:SPICE-alike analog simulator developed by Cadence.共27页3高精度高精度模拟模拟/射频射频电路仿真器电路仿真器l1、Spectre/SpectreRF(Cadence)l2、Hspice/HspiceRF(Synopsys)l3、Ads(Agilent 主要针对RF)l4、Eldo(Mentor Graphics)l5、Saber(Synopsys)共27页4数模数模混合信号混合信号仿真器仿真器l1、Spectre-Verilog(Cadence)l2、SMASH(Dolphin Integration)l3、Eldo(Mentor Gra
4、phics)l4、Harmony(Silvaco)l5、Saber(Synopsys)Why Mixed-Signal Simulation?共27页5System in the Real World共27页6Mostly Applied Method of Mixed-Signal Design系统分成若干个芯片，每个芯片分开设计，再经电路板整合。或者用SoC实现。共27页7IntegratedMixed-Signal Design共27页8Mixed-Signal Simulator 的基本结构的基本结构l以模拟电路仿真器为核心以模拟电路仿真器为核心 在处理数模混合电路时将数字部分等效为相
5、应的简化的模拟电路、或者采用解析函数来表示逻辑模块的行为，然后对整个系统采用模拟电路的方法进行模拟。优点：模拟结果精确、能处理的电路规模比较大，模拟速度也有显著提高。缺点：比逻辑模拟器还是慢很多。l同时包含模拟和数字两个仿真核同时包含模拟和数字两个仿真核 处理速度快，能处理的电路规模极大，但需要解决模拟仿真核和数字仿真核之间的通信问题；另外，由于数字逻辑仿真器和模拟仿真器的输入、输出数据是不一样的，还必须在模拟仿真核和数字仿真核之间实现模拟信号和数字信号的相互转换。Q&A共27页9Creating Analog BlockCreate the schematic view of analog
6、block,and create a symbol view for cell use共27页10Creating Digital Block共27页11Creating a Mixed-Signal Schematic共27页12Create Config View for SimulationThe mixed-signal simulation hierarchy is controlled by Hierarchy-Editor which must be defined with config viewcell name is top circuit name for simulat
7、ionview name will be set as configUse Create New File to create a new config view with Hierarchy-Editor共27页13Set New Configuration1.Choose Use Template sample information2.Choose spetreVerilog1233.Change the view name to schematic for simulation4.Click OK共27页14Open the Schematic Version of Config Vi
8、ewOpen the schematic version of the config view of mix from the Library manager共27页15Set Block Partition开启hierarchy editor设定所使用的cell view显示所使用的cell view 及其颜色设定Schematic editor 中的Hierarchy-Editor 及Mixed-Signal 两项Menu是由菜单Tools-Mixed Signal Opts.而产生的共27页16Check Block PartitionChange analog&digital stop
9、 views to match the stop views in your hierarchy editor(as below)共27页17Check Partition Results设定显示的颜色及项目显示所有模块划分的结果显示模拟电路模块显示数字电路模块显示混合信号电路模块显示无法归类的电路模块清除所有显示内容共27页18Partition RequirementlThe design must contain at least one analog component.lThe design must contain at least one digital component.lT
10、here must be with at least one interface net.lAnalog stimuli defined in the analog stimuli file cannot be used to drive digital net.lDigital stimuli defined in the digital stimuli file can not be used to drive analog net.lAny interface net must be identified before netlisting.共27页19Setup the analog/
11、digital interfaceSelect:Mixed-Signal-Interface Elements-Instancethis tool is used to configure how the digital block reads analog inputs and how digital outputs are seen by analog cells(effective A/D and D/A).共27页20Setup the analog/digital interfaceMOS_a2d:A2D_V0 低电平 A2D_V1 高电平 A2D_TX：voltage betwee
12、n V0 and V1 after TX will yield a logic XMOS_d2a：Model Parameters D2A_VL:input low voltageD2A_VH:input high voltageD2A_TR:rise time for low to highD2A_TF:fall time for high to low共27页21Setup Menu in Analog EnvironmentWith Setup window to define simulationinitialization setupChoose the simulatorDefin
13、e device model libraryDefine temperature共27页22Choosing Simulator/Directory/Host选择选择SpectreVerilog共27页23Choose Analysis TypeInvoke the analysissetting windowFor Mixed-Signalsimulation,onlytran is meaningfulSet the simulation timeCheck this box to enable this simulation共27页24Submit the SimulationExecute the simulation job with Run,or create the netlist with Netliststart simulation共27页25Results数字输出数字/模拟输入模拟输出共27页26THANK YOU!共27页27
