1、Computer Organization & ArchitectureChapter 15The IA-64 Architecture15.1 Motivationv 64-bit processor developed by Intel and HP v Basic concepts underlying IA-64 refers to as explicitly parallel instruction computing (EPIC) Explicit instruction-level parallelism Long and very long instruction words
2、Branch predication Speculative loading Software pipeliningv Itanium is first Intel productv Table 15.1 gives us key differences between IA-64 and a normal superscalar Superscalar vs. IA-64v New Architecture Not hardware compatible with x86 Now have tens of millions of transistors available on chip C
3、ould build bigger cache Diminishing returns Add more execution units Increase superscalaring “Complexity wall” More units makes processor “wider” More logic needed to orchestrate Improved branch prediction required Longer pipelines required Larger number of renaming registers required At most six in
4、structions per cycle Greater penalty for mispredictionvExplicit Parallelism Instruction parallelism scheduled at compile time Included with machine instruction Processor uses this info to perform parallel execution Requires less complex circuitry for parallel scheduling Compiler has much more time t
5、o determine possible parallel operations Compiler sees whole program15.2 General OrganizationvA generous number of registers 256 registers 128 for integer,logical,and general-purpose use 128 82bit for FPs and graphics use 64 1-bit predicate registers Used for predicate execution To support high degr
6、ee of parallelismvMultiple execution units 8 or more parallel unitsvSee fig.15.1General Organization for IA-64v IA-64 Execution Units I-Unit Integer arithmetic Shift and add Logical Compare Integer multimedia ops M-Unit Load and store Between register and memory Some integer ALU B-Unit Branch instru
7、ctions F-Unit Floating point instructions15.3 Predication, speculation and software pipelingvInstruction Format 128-bit bundle: 3 instructions and a template fields, see fig.15.2 The processor can fetch one bundle at a time Template field contains information that indicates which instructions can be
8、 executed in parallel The processor can look at multiple bundles to decide instructions in parallel The instructions are reorder and template is set by compilerIA-64 Instruction Word Format41v Predicated Execution Predication is a technique whereby the compiler determines which instructions may exec
9、ute in parallel In the process, the compiler eliminates branches from the program by using conditional execution For the conditional execution, a predication register is used for each way When the condition instruction is completed, cancel one way pipeline instructions See fig.15.3aIA64-predicationv
10、 Speculative load: the processor loads data from memory before the program needs it, to avoid memory latency Speculative load is another innovation in IA-64 Compiler rearrange the code so that loads are done as early as possible A load instruction in original program is replaced by two instructions:
11、 A speculative load A check instruction See fig.15.3bIA-64 Speculative LoadingLoop unrolling software pipeliningv Yi=xi+cv L1: ld4 r4=r5,4; add r7=r4,r9; st4 r6=r7,4 br.cloop L1Note: pipelining, but cannot parallelizing5 iterations in 7 cyclesld4 r32=r5,4 ; /cycle 0ld4 r33=r5,4 ; / 1ld4 r34=r5,4 / 2
12、add r36=r32,r9 ; / 2ld4 r35=r5,4 / 3add r37=r33,r9 / 3st4 r6=r36,4 ; / 3 ld4 r36=r5, 4 / 4 add r38=r34,r9 / 4 st4 r6=r37,4 ; / 4 add r39=r35,r9 / 5 st4 r6=r38,4 ; / 5 add r40=r36,r9 / 6 st4 r6=r39,4 ; / 6 st4 r6=r40,4 ; / 7Itanium Processor DiagramAdvanced load address tableMulti- Core Technologyv D
13、ual core: two operation cores integrated in a CPU Based on X86 architecture Idea comes from HyperThread AMD, Intelv AMD DCore: two cores integrated in a die Communication delay is very short Scalability is betterv Intel DCore: First generation:two CPU enveloped in a chip Dual CPU Multi-coreKey points Several advanced techniques in IA-64 Multi- Core Technology
