1、 11.VHDL simulation 11.1 Simulation 11.2 VHDL simulation of dataflow code 11.3 Simulation of structural VHDL11.4 The uninitialized logic value 11.5 Delay modeling11.6 Test benches 1 11.1 SimulationVHDL descriptions must be simulated to confirm that they behave as required.Simulation allows us to app
2、ly inputs,and then trace how the rest of the circuit evolves with time as the influence of the new inputs propagates through towards the outputs.We can then compare the predicted outputs for our design to the desired outputs.If there are no differences then we can conclude that our design is correct
3、.2 11.2 VHDL simulation of dataflow code Event A change to a signal that is scheduled to take place at a certain time is called an event.The VHDL simulation proceeds by manipulating an event queue.Event queueA VHDL statement only executes when a value on the RHS changes.1.Some terms on simulation3 1
4、1.2 VHDL simulation of dataflow code The VHDL description of a full adder ARCHITECTURE number3 OF fulladd IS SIGNAL n1,n2,n3,n4:STD_LOGIC;BEGIN n1=x XOR y;-Statement 1 sum=cin XOR n1;-Statement 2 n2=x AND y;-Statement 3 n3=cin AND x;-Statement 4 n4=y AND cin;-Statement 5 cout=n2 OR n3 OR n4;-Stateme
5、nt 6END ARCHITECTURE number3;2.Example for simulation4 11.2 VHDL simulation of dataflow code Assumed that all signals are initially at zero.Time=0It has a list of the present value for each signal,any new value that has been scheduled to take place in future,and the time at which the signal must ass
6、ume this new value.3.Process for simulation5 11.2 VHDL simulation of dataflow code All statements 1-6 are scanned simultaneously.The event on x triggers the execution of the statements:n1=x XOR y;n2=x AND y;n3=cin AND x;Time=10If the new value is different from the old value,it is placed on the even
7、t queue.6 11.2 VHDL simulation of dataflow code VHDL simulation uses an infinitesimal time intervalto keep track of the delays that happen to signals as they are assigned.At time 10+,n1 takes its new value,which triggers:sum=cin XOR n1;Time=10+7 11.2 VHDL simulation of dataflow code At time 10+2,sum
8、 takes its new value.Time=10+2There are no statements with sum on the RHS,so no further statements are triggered.8 11.3 Simulation of structural VHDLThe VHDL code for the adder is LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY adder IS PORT(x,y:IN STD_LOGIC_VECTOR(3 DOWNTO 0);cin:IN STD_LOGIC;sum:O
9、UT STD_LOGIC_VECTOR(3 DOWNTO 0);cout:OUT STD_LOGIC);END ENTITY adder;ARCHITECTURE structural OF adder IS SIGNAL carry:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN c0:entity work.fulladd(dataflow)PORT MAP(x(0),y(0),cin,sum(0),carry(1);9 11.3 Simulation of structural VHDL c1:entity work.fulladd(dataflow)PORT MA
10、P(x(1),y(1),carry(1),sum(1),carry(2);c2:entity work.fulladd(dataflow)PORT MAP(x(2),y(2),carry(2),sum(2),carry(3);c3:entity work.fulladd(dataflow)PORT MAP(x(3),y(3),carry(3),sum(3),cout);END ARCHITECTURE structural;ContinuedDuring simulation all statements are active at the same time,and will be trig
11、gered to execute and re-compute their output values if any of their input signals changes.10 11.4 The uninitialized logic value When a digital electronic device is switched on,all bits stored in flip-flops and memory will initially go to a random value which could be a 1 and could be a 0.This is the
12、 value that VHDL refers to as U.It is important for simulation to verify that these random initialization values do not corrupt the subsequent behavior of the device.Normally,the simulator will initialize all internal signals to U instead of 0 and trigger an event on all signals.1.The uninitialized
13、logic value U 11 11.4 The uninitialized logic value The initial condition of the queue is:Time=0At time 0+,signals n1 to n4 receive their new values.This triggers computing new values for sum and cout.2.Process for simulation12 11.4 The uninitialized logic value Time=0+At time 0+2,sum and cout recei
14、ve their new values.13 11.4 The uninitialized logic value In this case,the U value simply causes the internal signals and the output values to be unknown for an infinitesimal period of time,and has had no lasting effect on any of the signals.Time=0+214 11.5 Delay modelingReal logic gates have a dela
15、y:when we change the inputs,the corresponding output appears some time later.Exp1:a 2-input Ex-OR gate with a 5 ns gate delay LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY xor2 is PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);END ENTITY xor2;ARCHITECTURE delayed OF xor2 ISBEGIN c=a XOR b AFTER 5 NS;END A
16、RCHITECTURE delayed;15 11.5 Delay modelingSimulation of the XOR gate with delay 16 11.6 Test benches The goal of simulation is to verify that a design has the required functionality.This is accomplished by a VHDL test bench.1.Test benchesA test bench is a VHDL description that takes a copy of a desi
17、gn,applies test inputs to the design and compares the outputs from the design with the required outputs.If the actual outputs match the required outputs for all input conditions then the design is judged to be correct.17 11.6 Test benches The general appearance of a VHDL test bench ENTITY testbench
18、ISEND ENTITY testbench;ARCHITECTURE tb OF testbench IS Declare all the test signals that will be connect to the inputs and outputs of the device we are testingBEGIN Place one copy of the design under test,and wire its inputs and outputs up to test signals Generate test waveforms that are applied to
19、the inputs Observe the outputs from the design and compare them with the required results.Report if any discrepancies are found.END ARCHITECTURE tb;18 11.6 Test benches 2.The ASSERT statementThe ASSERT statement provides a way to tell the VHDL tools what conditions we believe ought to be true if the
20、 design is functioning correctly.Its syntax isASSERT condition REPORT message SEVERITY severityThe condition shows what should be happening.If the condition is false,then a message is printed,and an error is generated of the stated severity.The severity can be NOTE,WARNING,ERROR,or FAILURE.19 11.6 T
21、est benches 3.A test bench for the 4-bit adderTest bench for the 4-bit adder circuit20 11.6 Test benches Generate the inputs PROCESSBEGIN FOR I IN 0 TO 15 LOOP FOR J IN 0 TO 15 LOOP -Set the inputs to the adder TestIn1=CONV_STD_LOGIC_VECTOR(i,4);TestIn2=CONV_STD_LOGIC_VECTOR(j,4);END LOOP;END LOOP;E
22、ND PROCESS;21 11.6 Test benches The expected output is calculated by ExpectedResult TestIn1,y=TestIn2,cin=0,sum=AdderOut,cout=AdderCarry);PROCESS BEGIN FOR I IN 0 TO 15 LOOP FOR J IN 0 TO 15 LOOP -Set the inputs to the adder TestIn1=CONV_STD_LOGIC_VECTOR(i,4);TestIn2=CONV_STD_LOGIC_VECTOR(j,4);24 11
23、.6 Test benches Continued-Calculate what the output of the adder should be ExpectedResult=CONV_STD_LOGIC_VECTOR(i+j,5);-Wait until adder output has settled WAIT FOR 1 ns;-Check whether adder output matches expectation ASSERT ExpectedResult(3 DOWNTO 0)=AdderOut and ExpectedResult(4)=AdderCarry REPORT Adder output is incorrect SEVERITY WARNING;END LOOP;END LOOP;WAIT;END PROCESS;END ARCHITECTURE tb;25
