1、 SFF-8431簡介及簡介及SFI電氣參數測試電氣參數測試 AgendaIntroduction of SFF-8431SFF-8431 Standard Compliance Test of SFIEye Diagram Test by DSA8200The specification of SFF-8431 defines the electrical interfaces and their test methods between the SFP+module and host board for operation up to 11.1 GBd.The high speed ele
2、ctrical interface between the host and SFP+module is called“SFI”.SFI simplifies the module and leverages host based transmit pre-emphasis and host based receive equalization to overcome PCB and external media impairments.SFI typically operates with one connector at the module interface and up to abo
3、ut 200 mm of improved FR4 material or 150 mm of standard FR4.The electrical interface is based on high speed,low voltage AC coupled logic with a nominal differential impedance of 100.The SFP+specifications includes management,low speed signal,high speed signal,connector(defined by SFF-8083),mechanic
4、al(defined by SFF-8432),and appendices providing parameter and test board definitions,and implementation and measurement descriptions.The SFP+SUPPORTED STANDARDSn The module signal ground contacts VeeR and VeeT should be isolated from module case.n At host power up the host shall supply VccT and Vcc
5、R to the module within 100 ms of each other.n SFP+low speed signaling is based on Low Voltage TTL(LVTTL)operating with a module supply of 3.3 V+/-5%and with a host supply range of 2.38 to 3.46 V.n To avoid exceeding system power supply limits and cooling capacity,all modules at power up by default s
6、hall operate with 1.0 W.Hosts supporting Power Level II operation may enable a Power Level II module through the 2-wire interface.Power Level II modules shall assert the power level declaration bit of SFF-8472.Over long spans such as the 40km Ethernet extended reach(ER)long wavelength applications,t
7、he SFP+transceivers may require additional power consumption,especially at extreme operating conditions.Power Level I modules Up to 1.0 W Power Level II modules Up to 1.5 WGENERAL REQUIREMENTS The maximum power level is allowed to exceed the classified power level for 500 ms following hot insertion
8、or power up,or Power Level II authorization,however the current is limited to values given by the following table.The SFP+module shall meet ESD requirements given in EN61000-4-2,criterion B test specification such that units are subjected to 15 kV air discharges during operation and 8 kV direct cont
9、act discharges to the case.SFI signaling is based on differential high speed low voltage logic with AC coupling in the module.SFI was developed with the primary goal of low power and low electromagnetic interference(EMI).To satisfy this requirement the nominal differential signal levels are 500 mV p
10、-p with edge speed control to reduce EMI.n PCB LAYOUT RECOMMENDATIONSThe PCB traces are recommended by the specification to meet 10010 differential impedace with nominal 7%differential coupling.It is preferable to have the impedance tolerance be 5.Route differential pairs at least 8x their trace-wid
11、th from other traces.Avoid sharp angles in routing,chamfer corners.In order to avoid reflection,the recommended minimum trace length requirement is“1 inch”in FR4.When there must be vias on the high-speed differential signals,the 100 differential vias is recommended be used.And stubs due to vias must
12、 be avoided.The maximum SFI trace length recommend by the specification of SFF-8431.lTEST ENVIRONMENT REQUIREMENTS1.The bandwidth of measurement instrument shall be 12 GHz or above;2.Require AC coupled test equipment on all test ports；3.All SFI test equipment must have 50ohm single ended impedance；4
13、.Reference impedance for differential measurements is 100ohm,and the reference impedance for common mode measurements is 25ohm;5.Host compliance test board is required.nTEST METHODOLOGY AND MEASUREMENT A.HOST COMPLIANCE TESTA.1 Test point Host system transmitter and receiver compliance are defined b
14、y tests in which a Host Compliance Board is inserted in place of the SFP+module.The compliance points are B.A.2 Measurement setupA.2 TEST EQUIPMENTA.3 Host Transmitter Output Jitter and Eye Mask Specifications at B B.10GSFP+Cu DIRECT ATTACH CABLE 10GSFP+Cu cable assemblies are effectively constructe
15、d out of a pair of SFP+modules with the OE components replaced with copper cabling.The cable assembly shall incorporate DC blocking capacitors with at least 4.3 V rating on the RX side and with high pass pole of between 20 kHz and 100 kHz.The drain wire is connected to VeeT and to VeeR.The cable shi
16、eld directly connects the module A and B cases.B.1 10GSFP+Cu Direct Attach ConstructionB.2 SFP+Direct Attach Cable Test SetupB.3 10GSFP+Cu Cable Assembly Specifications at B and C A.Our Test EnvironmentFigure 1DSA8200 Digital Serial Analyzer DC to 65 GHz optical bandwidth;DC to 70+GHz electrical ban
17、dwidth,with up to 12.5 GHz triggering.Bandwidth is determined by the capabilities of the installed modules;CR125A Electrical Clock Recovery instrument100 Mb/s to 12.5 Gb/s continuous data rate coverage;Single-ended or differential 50 data inputs/outputs;DC coupled data through path;Insertion loss:-2
18、.6dB when 12GHz80E04 Electrical Sample Module SMA RF coaxial cable with up to 18G bandwidth and the insertion loss is 1.4dB/m when 10GHz.C.Installing Test EnvironmentCautionsDo NOT apply a signal outside the Maximum Input Voltage Swing;Always use a wrist strap when making signal connections;Discharg
19、e to ground any electrostatic charge that may be present on the center and outer conductors of cables before attaching the cables to the instrument;Never install or remove modules while the instrument is powered on;Do NOT transport or ship the instrument with modules installed;If possible,always use
20、 ESD protection module(80E02)along the test path,example,TDR test;Always disable the 80E04s TDR function when not use the TDR function.C.1 Acquainted with Our Instrumenta)DSA8200 Digital Serial Analyzerb)CR125A Electrical Clock Recovery instrumentc)80E04 Electrical Sampling Module with TDR function.
21、C.2 Eye Diagram Test Environment Setup of SFINotes：Please see the attached notes to set the eye diagram test setup.Notes:Confirm those check-box under“TDR”SETUPS is unchecked to disable the TDR functions on the test channel.1.Setting the Display StyleNotes:Select the Infinite Persistence on the“Disp
22、”and the“fast sampling”mode on the front panel.2.Setting triggerNotes:Select the External Prescaler as the trigger source.3.Setting Math as sourcesNotes：For differential signal eye test,subtract the two differential sources we using to define a math as the aimed signal source.4.Waveform DatabasesNot
23、es：Select the math we had defined as the waveform database and choose the infinite mode to display it.5.Mask SettingNotes：Select our aimed eye mask in the drop-down menu or import customer mask we had defined.3.Setting Measurements Notes：Select the signal source and set signal type to“NRZ”.Then,set
24、measurement we aimed to show on the screen,for example,eye height,eye width,Pk-Pk jitter,RMS jitter,and so on.6.Set a STOP Action7.Restart TestingThe propagation delay inherent in connecting cables and probes can result in inaccurate amplitude and time-correlated measurements.To obtain the best meas
25、urement and analysisresults from your instrument,you will need to remove skew and compensate the attenuations in the test environment.Quick Tipsn Minimize skew by using balanced cable pairs.n Measure and match your cables.TDR modules such as 80E04 allow you to measure cable delays with very high pre
26、cision.n Compensate the attenuations on the cables and peripherals(CR125A).For example,the nominal attenuation on the CR125A is-2.6dB and the coaxial cable is-0.7dB/m,we used one two 0.5m coaxial cable each channel,so,we should compensate 4.0dB/channel on our differential signal path.Notes：Use the vertical buttons to compensate the channel we used.Q&AThank you!
