1、第十三讲微处理器接口芯片设计实例 -可编程并行接口芯片设计实例曲阜师范大学电气信息与自动化学院本讲主要内容 8255的引脚及内部结构 8255的工作方式及其控制字 8255的结构设计 8255芯片的VHDL语言描述 8255芯片VHDL语言描述模块仿真8255的引脚及内部结构 外部引脚内部结构控制字 LIBRARY IEEE;LIBRARY IEEE;USE IEEE.STD_1164.ALL;USE IEEE.STD_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UN
2、SIGNED.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PPI ISENTITY PPI IS使用库 PORT(RESET,RD,WR,CS,A0,A1:IN STD_LOGIC;PA:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);PB:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);PCL:INOUT TD_LOGIC_VECTOR(3 DOWNTO 0);PCH:INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);D:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0
3、);END PPI;实体描述构造体描述 ARCHITECTURE RTL OF PPI IS SIGNAL INTERNAL_BUS_OUT:STD_ULOGIC_VECTOR(7 DOWNTO 0);SIGNAL INTERNAL_BUS_IN:STD_ULOGIC_VECTOR(7 DOWNTO 0);SIGNAL ST,AD,FLAG:STD_ULOGIC_VECTOR(1 DOWNTO 0);SIGNAL CTRREG:STD_ULOGIC_VECTOR(7 DOWNTO 0);SIGNAL PA_LATCH,Pb_LATCH,Pc_LATCH:CTRREG:STD_ULOGIC_VE
4、CTOR(7 DOWNTO 0);读进程 BEGIN PROCESS(RD,CS)Begin st=cttreg(3)&cttreg(0);if(cs=0and rd=0)then if(a0=0and a1=0and cttreg(4)=1)then internal_bus_in=pa;elsif(a0=0and a1=0and cttreg(1)=1)then internal_bus_in=pb;elsif(a0=0and a1=1and st=“01”)then internal_bus_in(3 downto 0)=pcl(3 downto 0);elsif(a0=0and a1=
5、1and st=“10”)then internal_bus_in(7 downto 4)=pch(3 downto 0);elsif(a0=0and a1=1and st=“11”and ctrreg(7)=1)then internal_bus_in（3 downto 0）=pcl(3 downto 0);internal_bus_in（7 downto 4）=pch(3 downto 0);process(cs,wr,reset)variable ctrregF:std_ulogic;variable bctrreg_v:std_ulogic_vector(3 downto 0);beg
6、in if(cs=0 and wr=0)then ad=a1&a0;ctrregF:=d(7);iternal_bus_out=d;end if;if(reset=1)then pa_latch=00000000;pb_latch=00000000;pc_latch=00000000;ctrreg=10011011 bctrreg_v:=0000;ctrregF:=0;elsif(wrevent and wr=1)then if(ctrregF=1and ad=11 and cs=0)then ctrreg=internal_bus_out;elsif(ctrreg(7)=1and ad=00
7、 and cs=0)then pa_latch=internal_bus_out;elsif(ctrreg(7)=1and ad=01 and cs=0)then pb_latch=internal_bus_out;elsif(ctrreg(7)=1and ad=10 and cs=0)then pc_latchpc_latch(0)pc_latch(1)pc_latch(2)pc_latch(3)pc_latch(4)pc_latch(5)pc_latch(6)pc_latch(7)pc_latch(0)pc_latch(1)pc_latch(2)pc_latch(3)pc_latch(4)
8、pc_latch(5)pc_latch(6)pc_latch(7)flag=11;end case;end if;end if;end process;process(pa_latch)begin if(ctrreg(4)=0)then pa=pa_latch;else pa=ZZZZZZZZ;end if;end process;process(pb_latch)begin if(ctrreg(1)=0)then pb=pb_latch;else pa=ZZZZZZZZ;end if;end process;process(pc_latch)begin if(ctrreg(0)=0)then
9、 pcl=pc_latch(3 downto 0);else pcl=ZZZZ;end if;end process;process(pc_latch)begin if(ctrreg(3)=0)then pch=pc_latch(7 downto 4);else pch=ZZZZ;end if;end process;end rtl;8255构造体设计 锁存器 Pa_latch a口输出锁存器 Pb_latch b口输出锁存器 Pcl_latch c口低4位输出锁存器 Pch_latch c口高4位输出锁存器 Ctrreg 方式控制字寄存器 Bctrreg 选择标志寄存器 三态缓冲器d、pa、
10、pb、pc 组合逻辑电路 End if;Else internal_bus_in=“ZZZZZZZZ”;End if;D=internal_bus_in;End process;读进程Std_logic_1164定义了一个9值模型，每个值为逻辑电平（0、1与未知）与强度（强制、弱、高阻、未定和无关）的组合，其中高阻、未定和无关只有一个电平值（未知）。其定义如下：Type Std_Ulogic is(U,未定(Uninitialized)X,强制未知(Forcing Unknown)0,强制0(Forcing 0)1,强制1(Forcing 1)Z,高阻(High Impedance)W,弱未知(Weak Unknown)L,弱0(Weak 0)H,弱1(Weak 1)-无关(Dont Care);
