1、One Laptop per Child The OLPC project has beenmaking news recently with its$100 Linux laptop intended for every child on earth.Libya just purchased 1.2 million of them(powered by a wind-up crank).Cool!Machine Structures Lecture 14 State Elements:Circuits that Remember QuickTime and aTIFF(Uncompresse
2、d)decompressorare needed to see this picture.QuickTime and aTIFF(Uncompressed)decompressorare needed to see this picture.laptop.org复习复习ISA是非常重要的一层抽象是非常重要的一层抽象硬件与软件间的协议硬件与软件间的协议时钟控制电路的脉冲时钟控制电路的脉冲电压是模拟量电压是模拟量analog,量化为量化为 0/1电路的延时是生活中不可避免的电路的延时是生活中不可避免的fact of life两种类型的电路两种类型的电路:无状态组合逻辑无状态组合逻辑(&,|,)状态
3、电路状态电路(如如,寄存器寄存器)Intro to hardware description languageVerilog Hardware Description LanguageVery Brief Verilog Introduction Verilog Example:4-input multiplexor Verilog Example:AccumulatorLast word(for now)on Verilog状态单元的用途状态单元的用途1.用于存储数值，存储时间是不定的用于存储数值，存储时间是不定的:寄存器文件寄存器文件(如如MIPS中的中的$1-$31)存储器存储器(cac
4、hes和主存和主存)2.帮助控制组合逻辑块间的信息流动帮助控制组合逻辑块间的信息流动.状态单元用于保存组合逻辑块的输入端的状态单元用于保存组合逻辑块的输入端的信息流动，以允许其有序地经过信息流动，以允许其有序地经过.累加器示例累加器示例希望希望:S=0;for(i=0;in;i+)S=S+Xi为何需要控制信息流动呢?假定假定:每个每个 X 值逐个地输入，每周期一个值逐个地输入，每周期一个.n 周期之后，和出现在周期之后，和出现在S端端.First tryDoes this work?无法工作无法工作Nope!原因原因#1 如何控制如何控制 for 循环的下一次迭代循环的下一次迭代?原因原因#2
5、 如何表示如何表示:S=0?FeedbackSecond tryHow about this?RoughtimingRegister is used to hold up the transfer of data to adder.寄存器细节寄存器细节内部结构内部结构?N个翻转器个翻转器“Flip-Flop”Flip-flop 名字的由来：因为其值在名字的由来：因为其值在0和和1间翻来翻间翻来翻去去 D 是是“data”,Q 是是“output”也称为也称为“d-type Flip-Flop”Flip-flop的时序是什么样的的时序是什么样的?(1/2)边沿触发（边沿触发（Edge-trigg
6、ered）d-type flip-flop 这是这是“正边沿触发正边沿触发”“在时钟信号的上升沿在时钟信号的上升沿,获得获得d的样值，并传给输出的样值，并传给输出.其它其它时间时间,忽略输入忽略输入d的值的值.”波形示例波形示例:Whats the timing of a Flip-flop?(2/2)边沿触发边沿触发 d-type flip-flop这是这是“正边沿触发正边沿触发”“在时钟信号的上升沿在时钟信号的上升沿,获得获得d的样值，并传给输的样值，并传给输出出.其它时间其它时间,忽略输入忽略输入d的值的值.”波形示例波形示例:Accumulator Revisited(proper t
7、iming 1/2)Reset input to register is used to force it to all zeros(takes priority over D input).Si-1 holds the result of the ith-1 iteration.Analyze circuit timing starting at the output of the register.Accumulator Revisited(proper timing 2/2)reset signal shown.Also,in practice X might not arrive to
8、 the adder at the same time as Si-1 Si temporarily is wrong,but register always captures correct value.In good circuits,instability never happens around rising edge of clk.Pipelining to improve performance(1/2)时间时间添加更多的寄存器来加速时钟频率.Note:delay of 1 clock cycle from input to output.Clock period limited
9、by propagation delay of adder/shifter.Pipelining to improve performance(2/2)Timing Insertion of register allows higher clock frequency.More outputs per second.有限状态机有限状态机(FSM)介绍介绍 有限状态机的原理有限状态机的原理 功能可以用功能可以用“状态变换状态变换图图”表示表示.有限状态机可以用组有限状态机可以用组合逻辑和寄存器等硬合逻辑和寄存器等硬件实现件实现.有限状态机示例有限状态机示例:连续连续3个个1FSM图图输出端连续出
10、现3个1的有限状态机假定状态变换由时钟控制，在每个时钟周期，机器检查输入，并转换到一个新的状态，且产生新的输出Hardware Implementation of FSM+=?Therefore a register is needed to hold the a representation of which state the machine is in.Use a unique bit pattern for each state.Combinational logic circuit is used to implement a function maps from present s
11、tate and input to next state and output.Hardware for FSM:Combinational LogicPSInputNSOutput000000001010010000011100100000101001Truth tableNext lecture we will discuss the detailed implementation,but for now can look at its functional specification,truth table form.General Model for Synchronous Syste
12、ms Collection of CL blocks separated by registers.Registers may be back-to-back and CL blocks may be back-to-back.Feedback is optional.Clock signal(s)connects only to clock input of registers.Peer InstructionA.HW feedback akin to SW recursionB.We can implement a D-Q flipflop as simple CL(And,Or,Not
13、gates)C.You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input.ABC1:FFF2:FFT 3:FTF4:FTT5:TFF6:TFT7:TTF8:TTTPeer Instruction AnswerA.HW feedback akin to SW recursionB.We can implement a D-Q flipflop as simple CL(And,Or,Not gates)C.You can build a FSM to signal when
14、an equal number of 0s and 1s has appeared in the input.ABC1:FFF2:FFT3:FTF4:FTT5:TFF6:TFT7:TTF8:TTTA.It needs base case(reg reset),way to step from i to i+1(use register+clock).True!B.D-Q has state,CL never has state!False!C.How many states would it have?Say its n.How does it know when n+1 bits have
15、been seen?False!“And In conclusion”Verilog is used to describe and simulate hardware Simple subset used in this class State elements are used to:Build memories Control the flow of information between other state elements and combinational logic D-flip-flops used to build registers Clocks tell us when D-flip-flops change Setup and Hold times important We pipeline long-delay CL for faster clock Finite State Machines extremely useful
