1、微处理器的核心技术 流水线处理 运算器高速化 RISC和CISC 超标量执行 乱序执行 分支预测 缓存 多核心1了解处理器Nehalem E5620 长流水线=15级 X86指令解释为微指令后乱序执行 等待执行的微指令放在Reserveration Station 多个ALU运算单元并发、乱序执行 Reorder Buffer中实现串行化 Instruction RetirementPipeline 示例：4级和8级的流水线Intel的长流水线Front End读入x86指令，每个时钟周期16字节x86指令解析为微指令（op）微指令（op）缓存乱序执行-1寄存器重命名微指令进入保留站分配临时寄
2、存器发射指令各种运算Load/StoreEUEUEU乱序执行-2存入临时寄存器EU中计算结果Load/Store按指令顺序写出结果指令生效，真正写入内存和物理寄存器触发具有数据依赖的指令执行指令量化分析 取指令，每个16字节/cycle X86指令解析为微指令 简单指令3条/cycle 复杂指令1条/cycle 保留站到EU的Port，总共6个P0，P1，P5到ALU单元P2，P3，P4到Load/Store单元Instruction Retirement，4条op/cycleDependency Chain长度指令优化 长流水线=15级 Branch prediction miss性能损耗大
3、 减少Branch prediction miss率 减少/消除conditional branch Bit运算代替比较 Comvg指令代替比较 充分发挥Intel处理器乱序执行的能力 避免指令间存在long dependency chain 避免指令间隐性的依赖关系，例如对eflags的依赖CPU内部各部件访问速度10充分利用寄存器#define LZ4_COPYSTEP(s,d)A64(d)=A64(s);d+=8;s+=8;#define LZ4_COPYPACKET(s,d)LZ4_COPYSTEP(s,d)#define LZ4_WILDCOPY(s,d,e)do LZ4_COPYP
4、ACKET(s,d)while(d32)r=4;else r=0;val=32;if(!(val16)r+=2;val=8;else val=24;r+=(!val);return r;12并行执行*op+=*ref+;*op+=*ref+;*op+=*ref+;*op+=*ref+;13消除Conditional Branch 如何消除这个if语句if(a 31;r=(mask&c)|(mask&d);Bit运算版本2int mask=(a-b)31;r=d+mask&(c-d);cmovg版本r=(a b)？c:d;分支可能性提示#define likely(expr)expect(exp
5、r)!=0,1)#define unlikely(expr)expect(expr)!=0,0)while likely(ipmatchlimit-(STEPSIZE-1)15The Blocking Technique16The Blocking Technique/Increasing memory usage improves compression ratio/Reduced memory usage can improve speed,due to cache effect/Default value is 14,for 16KB,which nicely fits into Int
6、el x86 L1 cache#define MEMORY_USAGE 14#define HASH_LOG(MEMORY_USAGE-2)#define HASHTABLESIZE(1 HASH_LOG)struct refTablesHTYPE hashTableHASHTABLESIZE;17memchrmagic_bits=(unsigned long int)0 x7efefefe 32)|0 xfefefeff;/*Set up a longword,each of whose bytes is C.*/charmask=c|(c 8);charmask|=charmask 16;
7、charmask|=charmask=sizeof(longword)longword=*longword_ptr+charmask;if(longword+magic_bits)&magic_bits)!=0)18memchr续 const unsigned char*cp=(const unsigned char*)(longword_ptr-1);if(cp0=c)return(_ptr_t)cp;.if(cp7=c)return(_ptr_t)&cp7;n-=sizeof(longword);19False sharing20对齐cachelinetypedef union GFAll
8、ctr_t gfa;char align_gfaERTS_ALC_CACHE_LINE_ALIGN_SIZE(sizeof(GFAllctr_t);ErtsAllocatorState_t;char*states=erts_sys_alloc(0,+ERTS_CACHE_LINE_SIZE-1);states=(UWord)states)&ERTS_CACHE_LINE_MASK)?(char*)(UWord)states)&ERTS_CACHE_LINE_MASK)+ERTS_CACHE_LINE_SIZE):(char*)states);21perf listRAW HARDWARE EV
9、ENT DESCRIPTOR Even when an event is not available in a symbolic form within perf right now,it can be encoded in a per processor specific way.For instance For x86 CPUs NNN represents the raw register encoding with the layout of IA32_PERFEVTSELx MSRs(see Intel(R)64 and IA-32 Architectures Software De
10、velopers Manual Volume 3B:System Programming Guide Figure 30-1 Layout of IA32_PERFEVTSELx MSRs)or AMDs PerfEvtSeln(see AMD64 Architecture Programmers Manual Volume 2:System Programming,Page 344,Figure 13-7 Performance Event-Select Register(PerfEvtSeln).22致谢 部分图片和代码来自鸣嵩 treelink比赛分享23多谢大家!Questions？QQ:526275新浪微博:淘宝褚霸Gtalk:24
