1、1 1 1Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu第八章第八章 CMOS时序逻辑电路时序逻辑电路第一节第一节 基本的双稳存储单元基本的双稳存储单元第二节第二节 锁存器和触发器锁存器和触发器第三节第三节 动态时序电路动态时序电路第四节第四节 移位寄存器移位寄存器实现存储的两种方式：实现存储的两种方式：1、存在电容上、存在电容上（动态）（动态）只能短时存储（毫秒量级）只能短时存储（毫秒量级）需要刷新需要刷新快速、简单、低功耗快速、简单、低功耗2、利用正反馈、
2、利用正反馈只要不断电则始终存储只要不断电则始终存储利用了正反馈，能够再生利用了正反馈，能够再生常用于较少变化的场合，常用于较少变化的场合，一般是时钟控制一般是时钟控制CombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clock period)第一节第一节 基本的双稳存储单元基本的双稳存储单元3 3 3Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu双稳电路双稳电路应用
3、最广泛应用最广泛的时序电路的时序电路单稳电路单稳电路非稳电路非稳电路最简单的是最简单的是环形振荡器环形振荡器4 4 4Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu基本的双稳存储单元基本的双稳存储单元 两个反相器的输入两个反相器的输入输出交叉耦合构成具有输出交叉耦合构成具有存储功能的双稳态电路存储功能的双稳态电路只有两个稳定状态，表示存只有两个稳定状态，表示存0和存和存1但这种单元无法实现状态控但这种单元无法实现状态控制，不实用制，不实用5 5 5Depart
4、ment of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu第二节第二节 锁存器和触发器锁存器和触发器锁存器在时钟等的控制下进行采样和保持，透明的锁存器在时钟等的控制下进行采样和保持，透明的 透明模式，当时钟为高透明模式，当时钟为高/低时，把输入信号传递到输出低时，把输入信号传递到输出Q，电位敏，电位敏感型电路感型电路触发器触发器(边缘触发边缘触发)在时钟变化沿控制下改变状态，不透明的，采在时钟变化沿控制下改变状态，不透明的，采样输入和改变输出是分离的样输入和改变输出是分离的 边缘敏感
5、电路，在时钟变化时对输入采样边缘敏感电路，在时钟变化时对输入采样 正沿触发正沿触发:0 1 负沿触发负沿触发:1 0 一般采用锁存电路构成一般采用锁存电路构成(e.g.,主从触发器主从触发器)Latch-up Flip Flop（FF）6 6 6Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu锁存器和触发器的对比锁存器和触发器的对比7 7 7Department of Microelectronics,PKUDepartment of Microelectron
6、ics,PKU，Xiaoyan LiuXiaoyan LiuNOR SR锁存器锁存器Q为正码输出端为正码输出端Q为反码输出端为反码输出端S为置位端为置位端R为复位端为复位端QRSQQSRQ,R、S不能同时为不能同时为18 8 8Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuNAND SR锁存器锁存器R、S不能同时为不能同时为09 9 9Department of Microelectronics,PKUDepartment of Microelectronic
7、s,PKU，Xiaoyan LiuXiaoyan Liu时钟控制的时钟控制的NOR SR锁存器锁存器时钟为高时，时钟为高时，S、R信号有效信号有效时钟为低时锁存原状态，时钟为低时锁存原状态，S、R信信号无效号无效101010Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu时钟控制的时钟控制的 CMOS JK LatchCK为低，锁存原状态，为低，锁存原状态，J、K没有控制没有控制作用，作用，CK为高为高J、K控制端有效控制端有效JK控制端消除了控制端消除了RS控
8、制中的不定（禁控制中的不定（禁止态）止态）JK0时锁存时锁存JK0时锁存时锁存J1,K0 置位；置位；J0，K1 复位复位J=K=1,状态翻转状态翻转111111Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu时钟控制的时钟控制的 CMOS D LatchS=R=Dclock数据通过数据通过数据保持数据保持121212Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiao
9、yan LiuXiaoyan Liu时钟控制的时钟控制的 CMOS D Latch131313Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu触发器触发器 FF触发器触发器(边缘触发边缘触发)在时钟变化沿控制下改变状态，不透明的，采样输在时钟变化沿控制下改变状态，不透明的，采样输入和改变输出是分离的。采用主从结构可以实现输入、输出分离。入和改变输出是分离的。采用主从结构可以实现输入、输出分离。SSRRQQ主触发器从触发器ck可以避免在可以避免在CK为高的有效期间
10、，为高的有效期间，控制端控制端S、R因状态多次变化而因状态多次变化而出现的不必要的状态翻转出现的不必要的状态翻转141414Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu采用静态存储和动态存储采用静态存储和动态存储相结合构成相结合构成 准静态主从触准静态主从触发器电路发器电路SRQQck151515Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXi
11、aoyan LiuDQckckckckckckckckD触发器触发器SDRQQDDckckckckckckckck有直接置位（有直接置位（SD）和直接复位（）和直接复位（RD）端的）端的D触发器触发器161616Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuSDDRDckckckckckckckTG1234TGTGTGVVDDDDckQQ171717Department of Microelectronics,PKUDepartment of Microele
12、ctronics,PKU，Xiaoyan LiuXiaoyan Liu D触发器基础上构成的触发器基础上构成的T触发器触发器QQTckckckckckckckckQTTQQTQTDT=0时保持时保持T1时翻转时翻转181818Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuclockInOutdatastableoutputstableoutputstabletimetimetimetsutholdtc-q触发器的时序要求触发器的时序要求T tc-q+tplog
13、ic+tsutsu数据建立时间，数据建立时间，thold数据保持时间数据保持时间191919Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu非理想两相时钟的问题非理想两相时钟的问题!clkclkIdeal clocks!clkclk非理想时钟，一般称非理想时钟，一般称为时钟歪斜为时钟歪斜clock skew1-1 overlap0-0 overlapDclkX!clk!Q!clkQclkBAP1P2P3P4I1I2I3I4竞争、紊乱竞争、紊乱 clk 和和!cl
14、k 同时为高同时为高(1-1 overlap)D 和和Q 间瞬时导通，间瞬时导通，引起竞争；而且引起竞争；而且B和和D同时驱动同时驱动Aclk 和和!clk 同时为低时同时为低时(0-0 overlap)，信号需要动态存储，信号需要动态存储212121Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu第三节第三节 动态时序电路动态时序电路实现存储的两种方式：实现存储的两种方式：1、存在电容上、存在电容上（动态）（动态）只能短时存储（毫秒量级）只能短时存储（毫秒量级
15、）需要刷新需要刷新快速、简单、低功耗快速、简单、低功耗2、利用正反馈、利用正反馈只要不断电则始终存储只要不断电则始终存储利用了正反馈，能够再生利用了正反馈，能够再生常用于较少变化的场合，常用于较少变化的场合，一般是时钟控制一般是时钟控制CombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT(clock period)222222Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Li
16、uVDDVDDPDNIn1In2In3VDDPUNOutVDDOutVDDPDNIn1In2In3VDDIn4In4VDD(a)-module(b)-moduleCombinational logicLatchnp CMOS中利用中利用C2MOS锁存锁存232323Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuT1T2I1I2QQMDC1C2!clkclkclk!clk!clkclkmaster transparentslave hold master hol
17、dslave transparent masterslave动态动态D 触发器触发器242424Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuT1T2I1I2QQMDC1C2!clkclkclk!clk!clkclk时钟歪斜问题时钟歪斜问题252525Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liuclk!clk!clkclkQ
18、MC1C2QDM1M3M4M2M6M8M7M5MasterSlave!clkclkmaster transparentslave hold master holdslave transparent ononoffoffononoffoff时钟歪斜不敏感的时钟歪斜不敏感的C2MOS触发器触发器262626Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuD锁存器的锁存器的时序要求时序要求D触发器的触发器的时序要求时序要求272727Department of Mic
19、roelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu有限状态机有限状态机 Finite State Machine流水流水线线 pipelineVLSI系统结构系统结构282828Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu时钟设计时的考虑时钟设计时的考虑目标：减少时钟的延迟时间并改善时钟的目标：减少时钟的延迟时间并改善时钟的上升、下降时间；减少时钟的歪斜。上升、
20、下降时间；减少时钟的歪斜。时钟的延迟时钟的延迟时钟出现的问题：时钟出现的问题：时钟歪斜时钟歪斜clock skew：希望相同的时钟边缘在空间上出希望相同的时钟边缘在空间上出现了变化现了变化时钟紧张时钟紧张 clock jitter：时钟边缘在时间上出现的变化时钟边缘在时间上出现的变化脉冲宽度的变化脉冲宽度的变化292929Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu时钟歪斜和紧张时钟歪斜和紧张tsk时钟歪斜，时钟歪斜，tjs时钟紧张时钟紧张时钟歪斜和紧张都将
21、影响时钟的有效周期时钟歪斜和紧张都将影响时钟的有效周期时钟歪斜将引起边缘竞争时钟歪斜将引起边缘竞争303030Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu产生非理想时钟的原因产生非理想时钟的原因313131Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu时钟的时钟的H分布分布改善时钟的非理想分布改善时钟的非理想分布 时钟设计是
22、高性能数字系统中的关键时钟设计是高性能数字系统中的关键323232Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiuDEC Alpha 21164(EV5)Clock Driversq300 MHz clock(9.3 million transistors on a 16.5x18.1 mm die in 0.5 micron CMOS technology)lsingle phase clockq3.75 nF total clock loadlExtensi
23、ve use of dynamic logic333333Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu第四节第四节 移位寄存器移位寄存器 shift register常用于乘法器常用于乘法器及浮点运算及及浮点运算及数据的串并转数据的串并转换等换等Data In控制控制 =Data Out移位数量移位数量移位方向移位方向移位类型移位类型移位移位寄存器寄存器343434Department of Microelectronics,PKUDepartment of
24、 Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu单向串入单向串入-串出移位寄存器串出移位寄存器SISOckckckckDDinoutD QQDQQD QQckrckckckDoutDinSerial Input Serial OutputSerial Input Parellel Output10000353535Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu单向串入单向串入-并出移位寄存器并出移位寄存器SIPODCKQ
25、QrrckQQDEDQQrrckQQDEDQQrrckQQDEDQQrrckQQDErinEckckckckDoutDSerial Input Parellel Output363636Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu双向移位寄存器双向移位寄存器DCKQQckDRIDLIDoutDoutDDLIRICCCC2211DRIDLIDoutDRIDLIDoutDRIDLIDout373737Department of Microelectronics,
26、PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu4位通用移位寄存器功能位通用移位寄存器功能保持、右移、左移、并入、复位保持、右移、左移、并入、复位p301SL012013013p2013011012012p1012010011011p001101SR010010DSSDSSQSSQSSDDSSQSSQSSQSSDDSSQSSQSSQSSDDSSQSSDSSQSSD383838Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoya
27、n LiuXiaoyan Liu4位通用移位寄存器逻辑图位通用移位寄存器逻辑图DCKQQRDCKQQRDCKQQRDCKQQRRckDSRS0S1Dp0Dp1Dp2Dp3DSLQ3Q2Q1Q0393939Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan LiurgtnopleftAiAi-1Bi-1BiAiAi-1rgtnopleftBiBi-1A1A0010A1A0A1A01000A1A1A0001A00移位器，移位器，shifter4-bit Barrel Shif
28、ter 4位筒式移位器位筒式移位器A0A1A2A3B0B1B2B3Sh1Sh2Sh3Sh0Sh1Sh2Sh3Example:Sh0=1 B3B2B1B0=A3A2A1A0 Sh1=1 B3B2B1B0=A3A3A2A1 Sh2=1 B3B2B1B0=A3A3A3A2 Sh3=1 B3B2B1B0=A3A3A3A3414141Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu记录脉冲的个数记录脉冲的个数加、减、可逆加、减、可逆同步、异步同步、异步计数器的模所计数的长
29、度，计数器的模所计数的长度，即级数器所经历的状态数即级数器所经历的状态数n个触发器最多经历个触发器最多经历2n个状态，则作为个状态，则作为二进制计数器级数长度为二进制计数器级数长度为N2n若计数长度若计数长度M小于小于2n，则为，则为M进制计数器，模为进制计数器，模为M的计数器的计数器424242Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu异步二进制计数器（分频器）异步二进制计数器（分频器）ripple binary counter DCKQQDCKQQDC
30、KQQckrQ0QQ12 ckQQ01Q2计数顺序：Q2 Q1 Q0434343Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu用用T触发器构成二进制加法计数器触发器构成二进制加法计数器rckQ001Q12Q2Q33TTTTVDDVout驱动方程：01230120101QQQTQQTQTT444444Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXi
31、aoyan Liu4位二进制可预置可逆计数器位二进制可预置可逆计数器PETQQckPPETQQckPPETQQckPPETQQckPPEckMQQ32PP23QP11PQ00COCIr454545Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu用用T触发器实现二进制可逆计数器触发器实现二进制可逆计数器PETQQckPPETQQckPPETQQckPPETQQckPMCI0120123010120010QQQMQQMQCTQQMQMQCTQMMQCTCTIIII464646Department of Microelectronics,PKUDepartment of Microelectronics,PKU，Xiaoyan LiuXiaoyan Liu产生进位产生进位/借位输出的电路借位输出的电路MQ0QQQ123CCIO0123IOQQQMQCC加法计数时产生进位输出减法计数时产生借位输出0123IOQQQQMCC
