1、1第七章第七章 MOS存储器存储器7.2 MOS存储器单元存储器单元2MOS存储器单元nDRAM单元nSRAM单元nROM单元3DRAMDRAM单元结构和工作原理单元结构和工作原理存储电容Cs=A(Cox+Cj)4DRAM单元工作过程M1CSWLBLCBLVDD2VTWLXsensingBLGNDWrite 1Read 1VDDVDD/2VDD/2X信息的写入信息的写入6信息的读取信息的读取102SSRVVVRBSOSBORBSV CV CVVCC11RBSSBRBSV CV CVVCC 预备动作：位线预充电 过程：字线高电平-门管导通-存储电容和位线电容发生电荷分享 X7n为了反映DRAM单
2、元读出特性，引入单元电荷传输效率的参数T 电荷传输效率电荷传输效率101011BBBSSSBSVVVTVVVC C由于位线电容比存储电容大很多，因此电荷传输效率远小于1 DRAM读操作存在读操作存在2个问题个问题:读出后单元信号被破坏读出后单元信号被破坏,读出信号微弱读出信号微弱解决办法解决办法:设置灵敏再生放大器设置灵敏再生放大器(S/R)RBSOSBORBSV CV CVVCC11RBSSBRBSV CV CVVCC8DRAM单元结构n性能优值：增加存性能优值：增加存储单元电容值储单元电容值n面积优值：减小单面积优值：减小单元占用面积元占用面积n利用立体结构在不利用立体结构在不增加平面面积
3、情况增加平面面积情况下，增加存储电容下，增加存储电容n利用高利用高K材料增加存材料增加存储电容储电容101011BBBSSSBSVVVTVVVC CMetal word linePolySiO2Field Oxiden+n+Inversion layerinduced byplate biasPoly9DRAM单元结构：沟槽电容n垂直方向，向下拓展空间Cell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi SubstrateTrench CellX10DRAM单元结构：叠置电容n垂直方向：
4、向上拓展空间Stacked-capacitor CellCapacitor dielectric layerCell plateWord lineInsulating LayerIsolationTransfer gateStorage electrode点点X11DRAM单元结构发展12MOS存储器单元nDRAM单元nSRAM单元nROM单元13S SRAMRAM单元结构和工作原理单元结构和工作原理n高阻多晶硅电阻负载的单元13问题：功耗与可靠性的矛盾14n解决电阻负载单元中功耗和可靠性的矛盾n优势：n只有泄漏电流引起的静态功耗 n保证单元存储信息可靠 14CMOSCMOS单元电路单元电路1
5、56-transistor CMOS SRAM Cell WLBLVDDM5M6M4M1M3M2BLQQVDDGNDQQWLBLBLM1M2M4M3M5M616CMOS SRAM 读操作WLBLVDDM5M6M4M1VDDVDDVDDBLQ=1Q=0CbitCbit17CMOS SRAM 写操作 BL=1BL=0Q=0Q=1M1M4M5M6VDDVDDWL18CMOSCMOS单元结构单元结构n TFT TFT负载的负载的CMOSCMOS单元单元19SRAM Characteristics20MOS存储器单元nDRAM单元nSRAM单元nROM单元21Read-Only Memory Cells
6、WLBLWLBL1WLBLWLBLWLBL0VDDWLBLGNDDiode ROMMOS ROM 1MOS ROM 222掩模编程的掩模编程的ROMROM单元单元n一个一个MOS管构成一个单元管构成一个单元n用制作用制作MOS管的某一次光刻版实现编程：管的某一次光刻版实现编程：n离子输入离子输入，有源区，引线孔，有源区，引线孔W0W1W2W3B1B2B3B023并联结构 ROMWL0VDDBL0WL1WL2WL3VbiasBL1Pull-down loadsBL2BL3VDD24并联结构 ROMWL0GNDBL0WL1WL2WL3VDDBL1Pull-up devicesBL2BL3GND25
7、并联结构 ROM 版图:接触孔编程PolysiliconMetal1DiffusionMetal1 on DiffusionCell(11l x 7l)VDDVDDWL 0VDDBL 0WL 1WL 2WL 3VbiasBL 1Pull-down loadsBL 2 BL 3VDD26串并联结构 ROMAll word lines high by default with exception of selected row只有选中字线的一行为只有选中字线的一行为低电平低电平，其他行为，其他行为高电平高电平WL0WL1WL2WL3VDDPull-up devicesBL3BL2BL1BL027串
8、并联ROM 版图Cell(5l x 6l)PolysiliconThreshold-alteringimplantMetal1 on Diffusion离子注入编程离子注入编程No contact to VDD or GND necessary;Loss in performance compared to NOR ROMdrastically reduced cell sizeWL 0WL 1WL 2WL 3VDDPull-up devicesBL 3BL 2BL 1BL 028并联结构ROM等效电路n字线电容、电阻nWire capacitance and gate capacitance
9、nWire resistance(polysilicon)n位线电容电阻nResistance not dominant(metal)nDrain capacitanceVDDCbitrwordcwordWLBLWL 0GNDBL 0WL 1WL 2WL 3VDDBL 1Pull-up devicesBL 2BL 3GND29减小字线延迟Metal bypassPolysilicon word lineK cellsPolysilicon word lineWLDriver(b)Using a metal bypass(a)Driving the word line from both sid
10、esMetal word lineWL(c)Use silicidesWL0GNDBL 0WL1WL2WL3VDDBL 1Pull-up devicesBL 2BL 3GND30Precharged MOS ROMWL0GNDBL0WL1WL2WL3VDDBL1Precharge devicesBL2BL3GNDpref31浮栅浮栅MOSMOS管构成的管构成的EPROMEPROMn 利用浮栅上的存储电荷改变利用浮栅上的存储电荷改变MOS管的阈值电压管的阈值电压 (a)EPROM (b)EEPROM (c)Flash32The Floating-gate transistorFloating g
11、ateSourceP-SubstrateGateDrainn+n+toxtoxDevice cross-sectionSchematic symbolGSD33Floating-Gate Transistor Programming0 V0 VDSRemoving programming voltage leaves charge trapped5 V5 VDSProgramming results in higher VT.20 V20 VDSAvalanche injection34A“Programmable-Threshold”Transistor“0”-state“1”-stateD
12、VTVWLVGS“ON”“OFF”IDW0W1W2W3B1B2B3B035FLOTOX EEPROMFloating gateSourceSubstratepGateDrainn1n1FLOTOX transistorFowler-Nordheim I-V characteristic2030 nm10 nm-10 V10 VIVGD36Flash EEPROMControl gateerasurep-substrateFloating gateThin tunneling oxidensourcendrainprogrammingMany other options 37并联结构 Flash
13、 的擦除过程SD12 VGcellarrayBL0BL1openopenWL0WL10 V0 V12 VWL0GNDBL 0WL 1WL 2WL 3VDDBL 1Pull-up devicesBL 2 BL 3GND38并联结构 Flash 写入过程SD12 V6 VGBL0BL16 V 0 VWL0WL112 V0 V0 V39并联结构Flash的读出过程5 V1 VGSDBL0BL11 V 0 VWL0WL15 V0 V0 V40串联结构 Flash MemoryUnit CellWord line(poly)Source line(Diff.Layer)GateONOFGGateOxide41串联结构 Flash MemoryWord linesSelect transistorBit line contactSource line contactActive areaSTI42Characteristics of ROM43MOS存储器单元nDRAM单元nSRAM单元nROM单元
