1、6.1嵌入式系统开发环境基本操作module decoder3_8(out,in); output7:0 out; input2:0 in; reg7:0 out; always (in) begin case(in) 3d0: out=8b11111110; /1111_1110=0000_0001,驱动LED正确显示3d1: out=8b11111101; /1111_1101=0000_00103d2: out=8b11111011; /1111_1011=0000_01003d3: out=8b11110111; /1111_0111=0000_10003d4: out=8b11101
2、111; /1110_1111=0001_00003d5: out=8b11011111; /1101_1111=0010_00003d6: out=8b10111111; /1011_1111=0100_00003d7: out=8b01111111; /0111_1111=1000_0000 endcase end endmodule6.2数字器件EDA设计计数器/Filename:counter_b/Function: add and sub function of 4 bit datamodule counter_b(clk,reset,mode,DS1,a,b,c,d,e,f,g,h
3、);output a,b,c,d,e,f,g,h;output DS1; /CS(chip select) signalinput clk,reset;input mode;wire DS1;wire a,b,c,d,e,f,g,h;reg 3:0 count;reg clk_reg;reg 31:0 count_reg1;initialbegincount_reg1=0;end assign DS1=1b0; /*div the clk*/ always(posedge clk) if(count_reg1=32d25000000) / count_reg div clk to genera
4、te clk_reg begin clk_reg=clk_reg; count_reg1=32d0; end else begin count_reg1=count_reg1+32d1; end /*self add and sub of count*/ always(posedge clk_reg or negedge reset) if(!reset) count=4d0; else begin if(mode) count=count+4b1; else count=count-4b1; end assign a,b,c,d,e,f,g,h=(DS1)?8bx:seg7(count),1
5、b0; function reg 6:0 seg7; input 3:0 in; case(in) 4b0000 :seg7=7b1111110; 4b0001 :seg7=7b0110000; 4b0010 :seg7=7b1101101; 4b0011 :seg7=7b1111001; 4b0100 :seg7=7b0110011; 4b0101 :seg7=7b1011011; 4b0110 :seg7=7b1011111; 4b0111 :seg7=7b1110000; 4b1000 :seg7=7b1111111; 4b1001 :seg7=7b1111011; 4b1010 :se
6、g7=7b1110111; 4b1011 :seg7=7b0011111; 4b1100 :seg7=7b1001110; 4b1101 :seg7=7b0111101; 4b1110 :seg7=7b1001111; 4b1111 :seg7=7b1000111; default :seg7=7bx; endcase endfunctionendmodule 6.3数字锁相环设计module clkgen(reset,clk,clk1,clk2);parameter para_1=50000000; /1hz 50Mhz/1hz=50Mparameter para_2=3125000; /
7、16hz 50MHZ/16HZ=3125000input reset;input clk; / original clkoutput clk1,clk2; / two new ,one for fin ,one for ID_clockreg clk1,clk2;reg 25:0cnt1,cnt2;/1011_1110_1011_1100_0010_0000_00=50M ,/*counter with mod=para_1*/always(posedge clk or negedge reset) begin if(!reset) begin cnt1=b0000; clk1=b0; end
8、else begin if(cnt1=para_1-1) / full begin cnt1=b0000; clk1=b0; end else if(cnt1=(para_1-1)/2) / half begin clk1=b1; / 50% duty cnt1=cnt1+1; endelse cnt1=cnt1+1; endend/*counter with mod=para_2*/always(posedge clk or negedge reset) begin if(!reset) begin cnt2=b0000; clk2=b0; endelse begin if(cnt2=par
9、a_2-1) / full begin cnt2=b0000; clk2=b0; end else if(cnt2=(para_2-1)/2) / half begin clk2=b1; / 50% duty cnt2=cnt2+1; endelse cnt2=cnt2+1; endendendmodule/程序二dpll.vmodule dpll (fin, fout, ID_clock, reset);parameter M = 32;parameter K = 8;parameter N = 16;parameter M2 = 5;/ log base 2 of Mparameter K
10、2 = 3;/ log base 2 of Kparameter N2 = 4;/ log base 2 of Ninput fin, ID_clock, reset; / input freqency, & resetoutput fout; / output wire reset, XOR_out, DN_UP, K_clock, u2, fout; /reg (K2-1):0 Kup, Kdn; / up/down counters reg / reg of reg Carry, Borrow, Toggle_FF, Carry_pulse, Borrow_pulse, advanced
11、, delayed;reg ID_out, ID_out_2, ID_out_4, ID_out_8, ID_out_16; / ID_out and those devided by 2,4,and 8reg Carry_new, Borrow_new; assign K_clock = ID_clock; / get the clk/fin and assign XOR_out = fin fout; / Phase detect,fin-the input f,u2-the output f;assign DN_UP = XOR_out;/ above 2 lines,either is
12、 ok, just for more choice /*KCounter* up or down/always(negedge K_clock or negedge reset) /use the same clkbeginif(!reset) /reset all; begin Kup = 0; Kdn = 0; Carry = 0; Borrow = 0; endelse /normal way begin if(DN_UP) Kdn = Kdn + 1; / DN_UP=1, then down, fout advance fin else Kup = Kup + 1; /up Carr
13、y = KupK2-1; / get the carry impulse , note: negedge Borrow = KdnK2-1; /get the borrow impulse ,note: negedge endend/*ID Counter*/ /always(posedge Carry or posedge ID_clock)always(posedge ID_clock) / add 1/2 clk to the original signalbegin if(!Carry) / no carry in begin Carry_new = 1; / original val
14、ue,no carry,only Carry_pulse = 0; end else if(Carry_pulse) / Carry=Carry_pulse=1, begin Carry_pulse = 0; / Carry_new = 0; end else if(Carry & Carry_new) / Carry=Carry_new=1,get a carry now and no carry before begin Carry_pulse = 1; /next poseedge, get 1, Carry_new = 0; / clear end else begin Carry_p
15、ulse = 0; Carry_new = 0; end /if(ID_clock) Carry_pulse = 0; /else Carry_pulse = 1;end/always(posedge Borrow or posedge ID_clock)always(posedge ID_clock) / delete 1/2 clkbegin if(!Borrow) / Borrow =0 begin /set Borrow_new = 1; Borrow_pulse = 0; end else if(Borrow_pulse) / begin Borrow_pulse = 0; Borr
16、ow_new = 0; end else if (Borrow & Borrow_new) begin Borrow_pulse = 1; Borrow_new = 0; end else begin Borrow_pulse = 0; Borrow_new = 0; end/ if(ID_clock) Borrow_pulse = 0;/ else Borrow_pulse = 1;endalways(posedge ID_clock or negedge reset)begin if(!reset) / reset begin Toggle_FF = 0; delayed = 1; adv
17、anced = 1; end else begin if(Carry_pulse) / Carry_pulse=1,get a carry now and no carry before begin advanced = 1; / Toggle_FF = !Toggle_FF; / Toggle_FF inverse end else if(Borrow_pulse) begin delayed = 1; / Toggle_FF = !Toggle_FF; / inverse end else if(Toggle_FF = 0) / begin if(!advanced) /no carry
18、or borrow when running Toggle_FF = !Toggle_FF; /inverse else if(advanced) / begin Toggle_FF = Toggle_FF; advanced = 0; end end else / begin if(!delayed) Toggle_FF = !Toggle_FF; / no borrow else if(delayed) begin Toggle_FF = Toggle_FF; delayed = 0; end end endendalways(ID_clock or Toggle_FF) begin if
19、(Toggle_FF) ID_out = 0; /Toggle_FF=1,keep 0 else begin if(ID_clock) ID_out = 0; /ID_clock=1, else ID_out = 1; endendassign u2 = ID_out; / /*NCounter*/ always(negedge ID_out or negedge reset)begin if(!reset) ID_out_2 = 0; /reset else ID_out_2 = !ID_out_2; /divided by 2endalways(negedge ID_out_2 or ne
20、gedge reset)begin if(!reset) ID_out_4 = 0; /ID_out_2 divided by 2 ,ID_out devided by 4 else ID_out_4 = !ID_out_4;endalways(negedge ID_out_4 or negedge reset)begin if(!reset) ID_out_8 = 0; /ID_out_4 divided by 2 ,ID_out devided by 8 else ID_out_8 = !ID_out_8;endalways(negedge ID_out_8 or negedge rese
21、t)begin if(!reset) ID_out_16 = 0; /ID_out_8 divided by 2 ,ID_out devided by 16 else ID_out_16 = !ID_out_16;endassign fout = ID_out_8; / the outputendmodule6.4字符LCD液晶显示控制/Filename:LCD.V/Function:display in two line: on the first line is time,the second is module LCD(clk,reset,oe,rs,rw,LCD_D);output 7
22、:0 LCD_D; /-data or commandoutput oe; /-LCD enableoutput rs; /-commmand or dara register select output rw; /-write or read enableinput clk; /-system clockinput reset;/-reset signalreg 7:0 cnt0;reg 7:0 LCD_D;reg oe;reg rs;reg rw;reg 7:0 RAM 23:0;reg clk0;reg clk_c;reg 7:0 count1;reg clk1;reg 31:0 cou
23、nt,count_reg;reg 3:0 state;reg 4:0 cnt;reg 4:0 i;reg 4:0 j;reg 4:0 k;reg 5:0 sec;reg 4:0 hour; /-24 hour clockreg 5:0 min;wire 3:0 hour_d,hour_u,min_d,min_u,sec_d,sec_u;parameter wait_state=4d0, /wait_state to the entry_set is the initialization of the LCD state1=4d1, state2=4d2, state3=4d3, state4=
24、4d4, state5=4d5, LCD_clear=4d6, /-clear the screen,delay of it must be more than 1.64ms entry_set=3d7, /-input format setting display_set=4d8, /-display format:on/off of the display?cursor on/off and flicker or not function_set=4d9, /-function setting:data bits?lines setting and character of display
25、 position1_set=4d10,/-initial loaction of first data write_data1=4d11, /-read data1 to LCD position2_set=4d12,/-location of second data write_data2=4d13, /-read data2 to LCD idle=4d14; /*div clk to 250KHz*/always(posedge clk or negedge reset) if(!reset) begincount1=8d0;clk1=1b0;end else if(count1=10
26、0-1) begincount1=8d0;clk1=clk1; end else count1=count1+8d1;always(negedge clk1 or negedge reset)/always(negedge clk or negedge reset) if(!reset) beginRAM0=4b0011,4h0; /-num on decimal bit (hour)RAM1=4b0011,4h0; /-num on unit bit (hour) RAM2=8h3a; RAM3=4b0011,4h0; /-num on decimal bit(minute)RAM4=4b0
27、011,4h0; /-num on unit bit (minute) RAM5=8h3a;RAM6=4b0011,4h0; /-num on decimal bit(second)RAM7=4b0011,4h0; /-num on unit bit (second)RAM8=8h77;RAM9=8h77;RAM10=8h77;RAM11=8h2E;RAM12=8h67;RAM13=8h65;RAM14=8h78;RAM15=8h69;RAM16=8h6E;RAM17=8h2E;RAM18=8h63;RAM19=8h6F;RAM20=8h6D;RAM21=8h2E;RAM22=8h63;RAM
28、23=8h6E; /-addresses if in RAM end else beginRAM0=4b0011,hour_d; RAM1=4b0011,hour_u; RAM2=8h3a; /-colonRAM3=4b0011,min_d; RAM4=4b0011,min_u; RAM5=8h3a; /-colonRAM6=4b0011,sec_d; RAM7=4b0011,sec_u; RAM8=8h77;RAM9=8h77;RAM10=8h77;RAM11=8h2E;RAM12=8h67;RAM13=8h65;RAM14=8h78;RAM15=8h69;RAM16=8h6E;RAM17=
29、8h2E;RAM18=8h63;RAM19=8h6F;RAM20=8h6D;RAM21=8h2E;RAM22=8h63;RAM23=8h6E; / -addressed of in RAM end /*div clk to 1000HZ clk0*/ always(posedge clk or negedge reset) begin if(!reset) begin clk0=1b0; count=32d0; end else if(count=32d2000) begin clk0=clk0; count=32d1; end else count=count+32d1; end /*div
30、 clk to 1HZ clk_c*/ always(posedge clk or negedge reset) begin if(!reset) begin clk_c=1b0; count_reg=32d1; end else if(count_reg=32d25000000-1) begin clk_c=clk_c; count_reg=32d1; end else count_reg=count_reg+32d1; end always(posedge clk0 or negedge reset) if(!reset) begin cnt=3b0; state=wait_state;
31、i=0; j=0; end else case(state)wait_state: begin cnt0=cnt0+1; if(cnt0=100) begin state =state1; cnt0=0; end else state=wait_state; end state1:begin oe=1b1; LCD_D=8b0011_1000; rs=1b0; /-command rw=1b0; /-write cnt030 & cnt0=35) oe=1b0; else oe=1b1; if(cnt0=70) begin state=state2; cnt0=0; end endstate2
32、: begin oe=1b1; LCD_D=8b0011_1000; rs=1b0; /-command rw=1b0; /-write cnt030 & cnt0=35) oe=1b0; else oe=1b1; if(cnt0=70) begin state=state3; cnt0=0; end endstate3: begin oe=1b1; LCD_D=8b0011_1000; rs=1b0; /-command rw=1b0; /-write cnt030 & cnt0=35) oe=1b0; else oe=1b1; if(cnt0=70) begin state=state4;
33、 cnt0=0; end endstate4:begin oe=1b1; LCD_D=8b0011_1000; rs=1b0; /-command rw=1b0; /-write cnt030 & cnt0=35) oe=1b0; else oe=1b1; if(cnt0=70) begin state=state5; cnt0=0; end end state5: begin oe=1b1; LCD_D=8b0000_1000; rs=1b0; /-command rw=1b0; /-write cnt030 & cnt0=35) oe=1b0; else oe=1b1; if(cnt0=7
34、0) begin state=LCD_clear; cnt0=0; end end LCD_clear: begin oe=1b1; LCD_D=8b0000_0001;/-clear screen rs=1b0; /-command rw=1b0; /-write cnt5d3 & cnt=5d12) oe=1b0; else oe=1b1; if(cnt=5d20) begin state=entry_set; cnt=0; end end entry_set: begin oe=1b1;LCD_D=8h06;/-cursor shifts right and LCD screen stay still after writing rs=1b0; /-command rw=1b0; /-write cnt5d8 & cnt=5d21) oe=1b0; else oe
