1、Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Chapter 2:MOS Device Physics2.1 General Considerations2.2 MOS I/V Characteristics2.3 Second-Order Effects2.4 MOS Device Models2.5 Appendix A:FinFETs2.6
2、Appendix B:Behavior of MOS Device as a Capacitor Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.2MOSFET as a Switch When gate voltage is high,device is on.Source and drain are interchangeable.But,-At
3、 what gate voltage does the device turn on?-How much is the resistance between S and D?-What limits the speed of the device?Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.3MOSFET Structure n-type MOS
4、(NMOS)has n-doped source(S)and drain(D)on p-type substrate(“bulk”or“body”).S/D junctions“side-diffuse”during fabrication so that effective length Leff =Ldrawn 2LD.Typical values are Leff 10 nm and tox 15.The S terminal provides charge carriers and the D terminal collects them.As voltages at the thre
5、e terminals changes,the source and drain may exchange roles.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.4MOSFET Structure MOSFETs actually have four terminals.Substrate potential greatly influence
6、s device characteristics.Typically S/D junction diodes are reversed-biased and the NMOS substrate is connected to the most negative supply in the system.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education
7、.5MOSFET Structure PMOS is obtained by inverting all of the doping types(including the substrate).Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.6MOSFET Structure In complementary MOS(CMOS)technologi
8、es both NMOS(NFET)and PMOS(PFET)are needed and fabricated on the same wafer.In todays CMOS,the PMOS is fabricated in an n-well,where the n-well is tied to the most positive supply voltage.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior writt
9、en consent of McGraw-Hill Education.7MOS Symbols Substrate is denoted by“B”(bulk).PMOS source is positioned on top since it has a higher potential than the gate.Most circuits have NMOS and PMOS bulk tied to ground and VDD,respectively,so we tend to omit the connections(b,c).Digital circuits tend to
10、incorporate“switch”symbols(c).Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.8Threshold Voltage As VG increases from zero,holes in p-substrate are repelled leaving negative ions behind to form a depl
11、etion region.There are no charge carriers,so no current flow.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.9Threshold Voltage Increasing VG further increases the width of the depletion region and th
12、e potential at the oxide-silicon interface.Structure resembles voltage divider consisting of gate-oxide capacitor and depletion region capacitor in series.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Educati
13、on.10Threshold Voltage When interface potential reaches sufficiently positive value,electrons flow from the source to the interface and eventually to the drain.This creates a channel of charge carriers(inversion layer)beneath the gate oxide.The value of VG at which the inversion layer occurs is the
14、threshold voltage(VTH).Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.11Threshold Voltage Where -MS is the difference between the work functions of the polysilicon gate and the silicon substrate.-k i
15、s Boltzmanns constant.-q is the electron charge.-Nsub is the doping density of the substrate.-ni is the density of electrons in undoped silicon.-Qdep is the charge in the depletion region.-Cox is the gate oxide capacitance per unit area.-si is the dielectric constant of silicon.Copyright 2017 McGraw
16、-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.12Threshold Voltage In practice,threshold voltage is adjusted by implanting dopants into the channel area during device fabrication.For NMOS,adding a thin sheet of p+increas
17、es the gate voltage necessary to deplete the region.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.13Threshold Voltage Turn-on phenomena in PMOS is similar to that of NMOS but with all polarities rev
18、ersed.If the gate-source voltage becomes sufficiently negative,an inversion layer consisting of holes is formed at the oxide-silicon interface,providing a conduction path between source and drain.PMOS threshold voltage is negative.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduct
19、ion or distribution without the prior written consent of McGraw-Hill Education.14Derivation of I/V Characteristics Where -Qd is the mobile charge density along the direction of current I.-v is the charge velocity.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distributio
20、n without the prior written consent of McGraw-Hill Education.15Derivation of I/V Characteristics Onset of inversion occurs at VGS=VTH.Inversion charge density produced by gate oxide capacitance is proportional to VGS VTH since for VGS VTH,charge placed on the gate must be mirrored by charge in the c
21、hannel,yielding a uniform channel charge density:Where WCox is the total capacitance per unit length.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.16Derivation of I/V Characteristics Channel potenti
22、al varies from zero at the source to VD at the drain.Local voltage difference between the gate and the channel varies from VG to VG VD.Charge density now varies with respect to x:,where V(x)is the channel potential at x.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or dist
23、ribution without the prior written consent of McGraw-Hill Education.17Derivation of I/V Characteristics Since -A negative sign is added because the charge carriers are negative for NMOS.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written
24、 consent of McGraw-Hill Education.18Derivation of I/V Characteristics VGSVTH is known as the“overdrive voltage.”W/L is known as the“aspect ratio.”If VDS VGSVTH,we say the device is operating in the“triode region.”.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distributi
25、on without the prior written consent of McGraw-Hill Education.19Derivation of I/V Characteristics If VDS 2(VGSVTH),then In this case,the drain current is a linear function of VDS so the path from source to drain can be represented by a linear resistor:Copyright 2017 McGraw-Hill Education.All rights
26、reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.20Derivation of I/V Characteristics If VDS VGSVTH,ID becomes relatively constant and we say that the device operates in“saturation region.”VD,sat =VGSVTH denotes the minimum VDS necessary for operatio
27、n in saturation.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.23Derivation of I/V Characteristics If VDS is slightly larger than VGSVTH,the inversion layer stops at x L,and the channel becomes“pinch
28、ed off.”As VDS increases,the point at which QD equals zero gradually moves towards the source.At some point along the channel,the local potential difference between the gate and the oxide-silicon interface is not sufficient to support an inversion layer.Copyright 2017 McGraw-Hill Education.All right
29、s reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.24Derivation of I/V Characteristics Electron velocity()rises tremendously as they approach the pinch-off point(where )and shoot through the depletion region near the drain junction and arrive at the
30、 drain terminal.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Since the integral becomes -ID is relatively independent of VDS if L remains close to L.The device exhibits a“square-law”behavior.25Deri
31、vation of I/V Characteristics Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.26Derivation of I/V Characteristics For PMOS devices,the equations become The negative sign shows up due to the assumption
32、 that drain current flows from drain to source,whereas holes in a PMOS flow in the reverse direction.VGS,VDS,VTH,and VGSVTH are negative for a PMOS transistor that is turned on.Since the mobility of holes is about the mobility of electrons,PMOS devices suffer from lower“current drive”capability.Copy
33、right 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.27Derivation of I/V Characteristics A saturated MOSFET can be used as a current source connected between the drain and the source.NMOS current sources injec
34、t current into ground while PMOS current sources draws current from VDD.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.28Derivation of I/V Characteristics VDS=VGSVTH=VD,sat is the line between satura
35、tion and triode region.For a given VDS,the device eventually leaves saturation as VGS increases.The drain is defined as the terminal with a higher(lower)voltage than the source for an NMOS(PMOS).Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prio
36、r written consent of McGraw-Hill Education.29MOS Transconductance Transconductance(usually defined in the saturation region)is defined as the change in drain current divided by the change in the gate-source voltage.gm represents the sensitivity of the device since a high value implies a small change
37、 in VGS will result in a large change in ID.Transconductance in saturation region is equal to the inverse of Ron in the deep triode region.Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.30MOS Transco
38、nductance Each expression for transconductance is useful in studying its behavior.Drain current and overdrive voltage are bias values.If a small signal is applied to a device with defined bias values,we assume the signal amplitude is small enough that the variation in transconductance is negligible.
39、Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.31MOS Transconductance To find the transconductance for the topology on the left with respect to VDS,-So long as VDS Vb VTH,M1 is in saturation,so ID is
40、 relatively constant,and therefore so is gm.-When M1 enters triode region (VDS Vb VTH),Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.32MOS Transconductance For PMOS,Copyright 2017 McGraw-Hill Educat
41、ion.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Originally,with the bulk of an NMOS tied to ground,the threshold voltage was defined as Decreasing the bulk voltage(VB)increases the number of holes attracted to the substrate connectio
42、n,which leaves a larger negative charge behind and makes the depletion region wider,increasing Qd and thus increasing VTH.This is known as the“body effect”or“back-gate effect.”33Second-Order Effects Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the
43、prior written consent of McGraw-Hill Education.With body effect,the expression which characterizes the dependence of threshold voltage on the bulk voltage is Where,-denotes the body effect coefficient.34Second-Order Effects Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or
44、distribution without the prior written consent of McGraw-Hill Education.35Second-Order Effects For example,lets find the drain current as bulk voltage varies from negative infinity to 0 given the topology on the left and that -If VX is sufficiently negative,VTH of M1 exceeds 1.2 V and the device is
45、off,therefore ,where -Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Body effect manifests itself whenever the source voltage varies with respect to the bulk potential.Given the topology on the left
46、and first ignoring body effect,as Vin varies,Vout follows the input because the drain current remains equal to I1,where36Second-Order Effects With body effect,as Vin,out become more positive,VSB increases,which increases VTH and thus Vin Vout must increase to maintain a constant ID.Copyright 2017 Mc
47、Graw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.Originally,when the device was in saturation region,drain current was characterized by The actual length of the channel(L=L L)is a function of VDS,which is an effect cal
48、led“channel length modulation.”1/L (1+L/L)/L,and L/L=VDS,where is the channel-length modulation coefficient”gives us 37Second-Order Effects Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.With the eff
49、ect of channel length modulation,the expressions derived for transconductance of the device that need modification are38Second-Order Effects Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGraw-Hill Education.39Second-Or
50、der Effects Knowing that -and keeping all other parameters constant,we can see that if the length L is doubled,the slope of ID vs.VDS is divided by four.This is due to .Copyright 2017 McGraw-Hill Education.All rights reserved.No reproduction or distribution without the prior written consent of McGra
