1、Chip-Package-System(CPS)Signal Integrity Co-AnalysisAgenda2 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017 Traditional Industry Trend for Memory Interface Performance Check ANSYS Chip-Package-System Signal Integrity Solutions Detail Flow Demonstration based on DDR DesignTraditional Performance Check of
2、DDRPHY ProviderManufacturing&MeasurementDesign multiple test IPs with required functions before mass production3 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Select IP with the best performanceNo IP meeting target performance,needs tremendous effort for root-causing,fixing designLate problem detectionC
3、ost Driven,Long TATThe Higher Performance,the more difficult release products on time Shadow area to SoC chip maker using 3rd part DDRPHYSimulation based Performance Checking Solution is necessaryTraditional System Level Signal IntegrityDirect connection btw IO and PKG without on-die PDNGenerally co
4、nsider only signal networks onpackageCant consider power-to-signal coupling Power supply noise induced delayIBIS or TransistorAccuracy Loss due to insufficient data,high probability of under design4 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Traditional IO Model for DDR Timing AnalysisIBISSimplestFas
5、test SimulationEasy to HandleConstant delay modelIndependent of supply voltageGlitch,non-convergenceTransistorMost AccurateGreatly longer simulation timeCant full bankanalysis due to capacityIdeal Chip Model isFaster than transistorFull Bank CapacityAs accurate as transistorIncluding IO circuit func
6、tion and intrinsic parasitic inside IO circuitIncluding Chip Layout(IO/Core PDN),IO decap cell5 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Chip Signal Model(CSM)for DDR Timing AnalysisIncluding RDL,on-die de-capsMultiple power domainsPer pad/bump broadband modelCompact model enables fast simulation i
7、n spiceCore PDNIOPDNCIOM(Chip IO Model)Non-linear device I/O buffer macro-modelSpice-level accuracy with full I/O bank capacityCaptures impact of P/G noise on signalLoad independentLayout and circuit IP encryptionAlso IBIS 5.0 Generation availableChip Signal ModelCdevESRIntrinsic capacitance extract
8、ion of IO Cell6 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Performance of CIOM and CSMCIOM enables faster and accurate analysis!CSM Measurement,biasedMeasurement,unbiasedCorrelation CSM vs.MeasurementComparison Xtor vs.CIOM vs.IBISCSM is well correlated with system level measurement7 2017 ANSYS,Inc.A
9、ugust 3,2017ANSYS UGM 2017IBIS/Xtor/CIOMOn-chip PDNIntrinsic Cap of IOChip Model Creation for Signal IntegrityChannel Connection&AnalysisCPS Signal Integrity for Chip DesignerAnsys Chip Signal ModelingJEDEC Timing AnalysisPG Noise AnalysisJitter AnalysisPackage/Board in SIwaveRLCG/S-parameterFor IO
10、CellCharacterizationIO Physical Design(GDS/LEF/DEF)IO Spice Netlist8 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017.Enables to predict power/signal Integrity performance check and optimization of DDRPHY.This flow is feasible to package designer who can get chip design infoCPS Signal Integrity for Packag
11、e DesignerIBIS/Xtor/CIOMOn-chip PDNIntrinsic Cap of IOChip Model Creation for Signal IntegrityChannel Connection&AnalysisJEDEC Timing AnalysisPG Noise AnalysisJitter AnalysisPackage/Board in SIwaveRLCG/S-parameter.Enables package/system designer to do full bank PDN aware signal integrity analysis.Pr
12、event under/over design due to CSM which has all chip level infoAnsys Chip Signal Modeling9 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Demo Video:Extract Parasitic of Board PDN via SIwave-CPA10 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017ANSYS Chip Signal Modeling Chip Model generation for DDR timing a
13、nd EMI Chip&System level signal Integrity simulation Target User:Package designer,Chip DDRPHY orIO designer Validation includes JEDEC compatible timing,noise,jitter,slew reporting covering single ended and differential type IOs Customized 3DIC,HBM,WLP(Wafer Level Package)target CSM generation&valida
14、tionANSYS CSMIO model (CIOM/IBIS/Xtor)generationOn-die PDN modelingModel Validation through system level analysisAdvanced CSM for System level EMI analysisIO-CPMgenerationChip Signal Model generation11 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017ANSYS CSM GUI OverviewCIOM Generation and ValidationDeca
15、p ModelingOn-die PDN parasitic extractionCSM Creation&Channel Connection for ValidationCSM Validation through system level analysisJitter Analysis based on Jedec Spec12 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Chip Signal Model Creation and Validation FlowCIOM Generation and ValidationIO Decap Mode
16、lingParasitic Extraction and Power IntegrityAnalysis of on-chip PDNCSM(Chip Signal Model)CreationSimulation env.set up for CSM validation1234513 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017What-if analysis for DDRPHY IO/Decap OptimizationIO/Decap/Core Instance can be newly defined or added;User-define
17、d cell instances are placed in DDRPHY.IO InstanceCore Instance14 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Decap Instance Enables to generate various types of CSM withdifferent optimization case;User can do performance check through channel simulation and select the best case.Demon Video:CSM Model C
18、reation of DDR Design15 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Channel Connection&Auto Simulation Test bench CreationCSM and all parasitic models from SIwave enables auto electrical connection between driver dies,Package and Board to receiver through CPP(Chip Package Protocol)header16 2017 ANSYS,
19、Inc.August 3,2017ANSYS UGM 2017New Virtual Compliance GUI Overview1.Each report cell can pop-up a waveform viewer window2.Right click menu can export HTML format report.Report list windowRight clickmenuCompliance test windowWaveform viewerWindowMessage windowTCL command window1217 2017 ANSYS,Inc.Aug
20、ust 3,2017ANSYS UGM 2017Reporting Tables OverviewVirtual Compliance ToolkitSelf DelayData Valid WindowNoisePeriod eye JitterSlew RateValid Transition TimeEye Diagram TimingWaveform TimingTrigger eye JitterClock Jitter18 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017RLC ModelPrototype Package&Board Chann
21、el ModelTransmission LineEnables to predict performance check at the early design stageInstantaneous impedance(Z0)is auto decided by RLC in the RLC ModelRLC&Z0 have been generated by geometrydefine in the Transmission Line ModelAs for multiple channel,mutual coupling effects can be defined between channels19 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017Demonstration Video20 2017 ANSYS,Inc.August 3,2017ANSYS UGM 2017感谢聆听感谢聆听
