1、1第五章第五章 数字集成电路基本模块数字集成电路基本模块5.3 加法器电路加法器电路2加法器n二进制加法n加法器结构设计n加法器电路设计3行波进位加法器-串行进位链进位逻辑求和逻辑G，P逻辑AiBiGiPiCi-1CiSi进位逻辑求和逻辑G，P逻辑A0B0G0P0C-1C0S0进位逻辑求和逻辑G，P逻辑A1B1G1P1C1S1.进位逻辑求和逻辑G，P逻辑AnBnGnPnCn-1CnSn.Generate(G)=ABPropagate(P)=ABB 4 配有超前进位链的加法器配有超前进位链的加法器w 多位加法器可以分成4位一组配进位链;w 用第二层进位链产生组进位输出5Carry-Lookahe
2、ad AdderiiiiiiiiiijgpppgppgpgG123123233iiiijppppP123jiijcPGc4)1(4计算计算p,g信号模块信号模块计算组进位计算组进位P，G输出组进位信号输出组进位信号C4(j+1)aibiCinCjGjPjai+1bi+1gi+1pi+1gipiai+2bi+2ai+3bi+3gi+1pi+1gi+1pi+1C4(j+1)C4j+1C4j+2C4j+3P,G Group6超前进位超前进位:电路结构电路结构333233232132103210inCGP CGP GP P GP P PGP P P P Cw 公式加括号。公式加括号。w 四位一组四位一
3、组CLACLA逻辑逻辑w 一级门实现，扇入较大一级门实现，扇入较大7Two-Levels of Logic Implementation of the Carry Block（最大扇入5）8Three-Levels of Logic Implementation of the Carry Block(限制扇入)进位逻辑电路结构9iiCBACBAS)()(PCGCCABACBACiioino)()(n进位逻辑可以用与或逻辑实现，也可以进位逻辑可以用与或逻辑实现，也可以用多路选择器实现用多路选择器实现n与或逻辑适合用静态与或逻辑适合用静态CMOSCMOS，多路器适，多路器适合传输门逻辑合传输门逻辑
4、TCGCCiioT=A+B10()()SA B CAB C()()COAB CA B A只有只有2020个个MOSFETMOSFET构成！构成！用传输门实现全加器用传输门实现全加器VDDABYABABABA B11一种静态一种静态CMOSCMOS进位链电路进位链电路333233232132103210inCGPCGPGPPGPP PGPP PPC12进位链：多输出多米诺进位链：多输出多米诺VDDC0PPP123PGGG123GCCCC3210in0333233232132103210inCGPCGPGPPGPP PGPP PPCManchester 进位链KiPiCiCi+1clkKill(K
5、)=A BPropagate(P)=A BCo=g+pCiP=a xor b!Co=!(g+pCi)=!a!b+(!a+!b)!C说明如果操作数和进位说明如果操作数和进位信号都取反，则进位输信号都取反，则进位输出为正确结果取反出为正确结果取反Generate(G)=AB 4-bit MCC AdderKP!C0clkKPKPKP&A0B0A1B1A2B2A3B3S0S1S2S3!C1!C2!C3!C4delay is roughly proportional to n*2(as n pass transistors are connected in series)so usually grou
6、p 4 stages together and buffer the carry chain with an inverter between each group15Manchester Carry ChainP0Ci,0P1G0P2G1P3G2P4G3G4VDDImplement P with pass-transistorsImplement kill(delete)with pull-downUse dynamic logic to reduce the complexity and speed upVDDC0PPP123PGGG123GCCCC3210in0本节总结n二进制加法基础二进制加法基础n加法器结构加法器结构n加法器电路加法器电路16
