1、第四章 多电压域设计技术（Multi-Voltage Domain）4.1 4.1 多电压域设计多电压域设计 VLSIVLSI发展的一个重要趋势是发展的一个重要趋势是SOCSOCu 工艺的进步使工艺的进步使SOCSOC成为可能；成为可能；u 设计复杂度的提高需要新的设计方法设计复杂度的提高需要新的设计方法u SOC SOC中各部分性能要求不尽相同，可工作在不同电中各部分性能要求不尽相同，可工作在不同电压下，性能要求高的工作的高电压域，反之。压下，性能要求高的工作的高电压域，反之。u 同一部分根据其工作负荷也可工作在不同电压同一部分根据其工作负荷也可工作在不同电压工作电压可以有不同变化方式工作电
2、压可以有不同变化方式 Static Voltage Scaling (SVS): different blocks or subsystems are given different,fixed supply voltages.（最简单的多电压域设计） Multi-level Voltage Scaling (MVS): an extension of the static voltage scaling casewhere a block or subsystem is switched between two or more voltage levels. Onlya few, fixed
3、, discrete levels are supported for different operating modes. Dynamic Voltage and Frequency Scaling (DVFS): an extension of MVS where alarger number of voltage levels are dynamically switched to follow changingworkloads. Adaptive Voltage Scaling (AVS): an extension of DVFS where a control loop isus
4、ed to adjust the voltage.u 就是最简单的就是最简单的 multi-voltage设计（设计（SVS）也）也给设计增加了难度给设计增加了难度 Level shifters. Signals that go between blocks that use different power rails often require level shifters Characterization and STA. With a single supply for the entire chip, timing analysis can be done at a single pe
5、rformance point. The libraries are characterized for this point, and the tools perform the analysis in a straight-forward manner. With multiple blocks running at different voltages, and with libraries that may not be characterized at the exact voltage we are using, timing analysis becomes much more
6、complex Floor planning, power planning, grids. Multiple power domains require more careful and detailed floorplanning. The power grids become more complex. Board level issues. Multi-voltage designs require additional resources on the board additional regulators to provide the additional supplies. Po
7、wer up and power down sequencing. There may be a required sequence for powering up the design in order to avoid deadlock. 高电压电源推低电压单元一般不会有问题 但时序参数不准，因库单元的时序参数是针对同电位的驱动和接收电路的，驱动端过驱动的时序最好专门单元4.2 Level Shifter 低低推高时会出现P、N管同时导通，必须用Level ShifterSuch “up-shifting” level converters require two supply rails
8、 and typically share a common ground. The well structures cannot be joined together but must be associated with the supplies independently.高推低时，高推低时，Level Shifter使用低电压，故使用低电压，故一般放在低电压域，因其使用低电压一般放在低电压域，因其使用低电压 4.3 Level Shifter Placement两电压域的模块距离较远时两电压域的模块距离较远时 ，可插入，可插入Buffer，BUFFER使用高电压使用高电压低推高时，低推高
9、时，Level Shifter一般放在高电压域，但因其一般放在高电压域，但因其使用高、低两个电压使用高、低两个电压 ，低压要象信号线一样连出，低压要象信号线一样连出Since the output driver requires more current than theinput stage, we place the level shifter in the 1.2V domain.placing the level shifters in the destination domainClock Skew静态时序分析：都要针对多电压域进行4.4 多电压设计时的时序问题多电压设计时的时序问题
10、第五章 漏电流控制技术The Power Crisis from IntelLeakage Power is catching up with the active power in nano-scaled CMOS circuits.The Power Crisis from IBM低压设计的问题：漏电流低压设计的问题：漏电流为什么要低电压设计？为什么要低电压设计？l小尺寸器件的要求小尺寸器件的要求l漏端热载流子退化临界电场漏端热载流子退化临界电场 Em0.2MV/cmEm0 时VG0 相当于VGSVs 结论l串联堆叠管越多漏流越小l不通的管子位置越低（靠近地）漏流越小l插入高Vth管对降低
11、漏流大有好处 原因ZLa ( kT )22 q2 ni NA21- exp(-qVD/ kT)exp(qS / kT)(qS / kT)1/2n Ci三、双域值晶体管电路三、双域值晶体管电路Nodes in critical pathNodes with low VthNodes with high Vthabcd高高Vth升高到一定值时静态功耗反而上升是因为更少的电路可以用高升高到一定值时静态功耗反而上升是因为更少的电路可以用高Vth1Vth2VthuW63.2126.3189.5双域值晶体管电路的扩充 VTCMOSVTCMOS电路电路l三端器件和四端器件三端器件和四端器件l两种电路技术两种
12、电路技术 通过通过SSBSSB和和LCMLCM组成反馈回路，补偿组成反馈回路，补偿VtVt的的变化变化 SBB self-substrate biasSBB self-substrate bias LCM leakage-current monitorLCM leakage-current monitor 通过电子开关控制衬底在通过电子开关控制衬底在STANDBYSTANDBY和和ACTIVEACTIVE模式时接不同偏压模式时接不同偏压四、衬底偏置四、衬底偏置/可变域值晶体管电路可变域值晶体管电路At 65nm and below, the body-bias effect decreases
13、, reducing the leakage control benefits. TSMC has published information pointing to a factor of 4 reduction at 90nm, and only 2 moving to 65nm . Consequently, substrate biasing is predicted to be overshadowed by power gating. VTCMOS电路l三端器件和四端器件l两种电路技术 通过SSB和LCM组成反馈回路，补偿Vt的变化SSB：self-substrate biasLC
14、M：leakage-current monitor 通过电子开关控制衬底在STANDBY和ACTIVE模式时接不同偏压SPR：standby power reduction降低功耗技术汇总降低功耗技术汇总各种功耗优化技术的效果各种功耗优化技术的效果低功耗物理设计Floorplanning with multiple power domainsPower delivery, through power planning and routingInsertion of power gating for low-power shut-offPlacement, including placement
15、 of level shifter, isolation, and SRPG cellsOptimization, including multiple threshold voltage (Multi-Vth) optimization, as well as multiple supply voltage (MSV) optimizationClock tree synthesis, ensuring the clock tree is well balanced and optimized for powerEfficient routing, because the shorter the route length, the less power is dissipated, while timing and signal integrity must be preservedAnalysis and verification, or signoff power analysis, to make sure power consumption is consistent with estimation, and that timing and IR drop are under control低功耗物理设计低功耗物理设计
