课件:数字逻辑7-3.ppt

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1、 FSM design:Sequence detectorChapter 7Finite state machine designSequence detector designOutput 1 only when input sequence be 1011 How to set the states?Sequence detector designs0 initial states1 get 1 bit 1;s2 get 2 bits 10;s3 get 3 bits 101;s4 get 4 bits 1011,output 1Set n+1 states to detect an n-

2、bits sequenceTransition of the stateSequence detector designSome guidelines for state assignmentuThe code for initial state should be easily reset;uThe code for neighboring state should be neighboring,frequently used states should be first considered.Sequence detector designSequence detector designT

3、ransition/output tableTransition list and transition tableSequence detector designSequence detector designHold the output until feedback If Y=1 and R=1,then return to initial stateSequence detector designHold the output until feedback Moore output and mealy outputSequence detector designHow to set t

4、he states for mealy design?Sequence detector designs0 initial states1 get 1 bit 1;s2 get 2 bits 10;s3 get 3 bits 101;If A=1 in state s3,then output 1Set n states to detect an n-bits sequenceSequence detector designState diagram and transition/output tableRisk for mealy output designSequence detector

5、 designSequence detector designMoore design for successive sequence detectSequence detector designMoore design for sequence detectSingle sequence detectsuccessive sequence detectSequence detector designMoore design for sequence detectSingle sequence detectsuccessive sequence detectSequence detector designOverlap sequence detect:moore designSequence detector designOverlap sequence detect:moore designSequence detector designOverlap sequence detect:mealy design

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