EDA技术与VHDL实用教程代码代码-5.docx

1、第五章 典型电路的VHDL设计例5-1：全加器的VHDL描述。全加器的逻辑函数式：S = A B CCY = AB+AC+BClibrary IEEE;ENTITY FullAdder isPORT(A,B,C: IN Std_Logic; CY : OUT Std_Logic； S : OUT Std_Logic);END FullAdder;ARCHITECTURE a OF FullAdder ISBEGIN S = A Xor B Xor C; CY = (A and B) OR (A and C) OR (B and C);End a; 例5-2：图5-1逻辑图的VHDL描述ARCH

2、ITECTURE a OF eqcomp4 IS Component AND4 Port (a, b, c, d: INStd_Logic; y: OUTStd_Logic); End Component; Component XNOR2 Port (M, N :IN Std_Logic;P :OUT Std_Logic ); End Component; signal X: Std_Logic_Vector(3 to 0);BEGIN U0: XNOR2 Port Map (A(0),B(0),X(0); U1: XNOR2 Port Map (A(1),B(1),X(1); U2: XNO

3、R2 Port Map (A(2),B(2),X(2); U3: XNOR2 Port Map (A(3),B(3),X(3); U4: AND4 Port Map (X(0),X(1),X(2),X(3), Y );END a;例5-3：八线-三线编码器的VHDL程序LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Coder IS PORT ( I : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

4、EN : IN STD_LOGIC ; Y : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0) ;END Coder ;ARCHITECTURE a OF Coder ISSIGNAL Sel: STD_LOGIC_VECTOR(8 DOWNTO 0);BEGIN Sel Y Y Y Y Y Y Y Y Y = 000 ; -包含EN=0的情况END a ;例5-4：38 译码器的VHDL程序LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_U

5、NSIGNED.ALL;ENTITY encoder IS PORT ( A : IN STD_LOGIC_VECTOR( 2 DOWNTO 0) ; EN : IN STD_LOGIC ; Y : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0) ;END encoder;ARCHITECTURE a OF encoder ISSIGNAL sel: STD_LOGIC_VECTOR( 3 DOWNTO 0) ;BEGINsel = EN & A; -将EN、A2、A1、A0合并以简化程序WITH sel SELECT Y= 00000001 WHEN 1000, 0000

6、0010 WHEN 1001, 00000100 WHEN 1010, 00001000 WHEN 1011, 00010000 WHEN 1100, 00100000 WHEN 1101, 01000000 WHEN 1110, 10000000 WHEN 1111, 00000000 WHEN OTHERS ; -包含EN=0的情况END a ;5.2 计数器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter IS PORT (clk, clr: IN

7、STD_LOGIC;Num:BUFFER integer RANGE 0 TO 9);END counter;ARCHITECTURE rtl OF counter ISBEGINPROCESS(clr,clk)BEGIN IF (clr=1) THEN -异步复位 Num=0;ELSIF rising_edge(clk) THEN IF Num=9 THEN Num=0; ELSE Num=Num+1; END IF; END IF;END PROCESS;END rtl;5.2.2.同步可逆计数器例5-6：可逆计数器（加减计数器）LIBRARY IEEE;USE IEEE.STD_LOGI

8、C_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; PORT (clk,clr,updn: IN STD_LOGIC; qa,qb,qc,qd,qe,qf: OUT STD_LOGIC);END updncount64;ARCHITECTURE rtl OF updncount64 IS SIGNAL count_6: STD_LOGIC_VECTOR(5 DOWNTO 0 );BEGIN qa=count_6(0); qb=count_6(1); qc=count_6(2); qd=count_6(3); qe=count_6(4); qf=count_6

9、(5);PROCESS(clr,clk)BEGIN IF (clr=0) THEN Count_6=”000000”; ELSIF (clkEVENT AND clk=1) THEN IF (updn=1 ) THEN count_6=count_6+1; ELSE count_6=count_6-1; END IF; END IF;END PROCESS;END rtl;例5-7：用VHDL设计一个模为60，具有异步复位、同步置数功能的BCD码计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL

10、; ENTITY CNT60 IS PORT(CI:IN STD_LOGIC; -计数控制 NRESET:IN STD_LOGIC; -异步复位控制 LOAD:IN STD_LOGIC; -置数控制 D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); -待预置的数 CLK:IN STD_LOGIC; CO:OUT STD_LOGIC; -进位输出 QH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);-输出高4位 QL:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);-输出低4位END ENTITY CNT60;ARCHITEC

11、TURE ART OF CNT60 IS BEGIN CO=1WHEN(QH=0101AND QL=1001AND CI=1)ELSE0; -进位输出的产生 PROCESS(CLK,NRESET) IS BEGINIF (NRESET=0)THEN -异步复位 QH=0000; QL=0000; ELSIF(CLKEVENT AND CLK=1)THEN -同步置数 IF (LOAD=1)THEN QH=D(7 DOWNTO 4); QL=D(3 DOWNTO 0);ELSIF(CI=1)THEN -模60的实现 IF (QL=9)THEN QL=0000; IF(QH=5)THEN QH=0

12、000; ELSE QH=QH+1; -计数功能的实现 END IF;ELSE QL=QL+1; END IF; END IF; END IF; END PROCESS;END ARCHITECTURE ART;5.3分频器的VHDL设计例5-8：偶数分频器的VHDL源程序Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity fdiv is generic(N: integer:=6); -rate=N，N是偶数 port( clk

13、in: IN std_logic; clkout: OUT std_logic );End fdiv;Architecture a of fdiv is signal cnt: integer range 0 to n-1;Begin process(clkin) -计数 begin if(clkinevent and clkin=1) then if(cntn-1) then cnt = cnt+1; else cnt = 0; end if; end if; end process; process(cnt) -根据计数值，控制输出时钟脉冲的高、低电平 begin if(cntn/2) t

14、hen clkout = 1; else clkout = 0; end if; end process;End a; 例5-9：常用的偶数分频器的VHDL程序Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity fdiv is generic(N: integer:=6); -rate=N，N是偶数 port( clkin: IN std_logic; clkout: OUT std_logic );End fdiv;Archit

15、ecture a of fdiv is signal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clkin) begin if(clkinevent and clkin=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clkout = temp;End a;例5-10：奇数分频器的VHDL源程序Library ieee;Use ieee.std_log

16、ic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity fdiv is generic(N: integer:=5); -rate=N，N是奇数 port( clkin: IN std_logic; clkout: OUT std_logic );End fdiv;architecture a of fdiv is signal cnt1, cnt2: integer range 0 to N-1;begin process(clkin) begin if(clkinevent and cl

17、kin=1) then -上升沿计数 if(cnt1N-1) then cnt1 = cnt1+1; else cnt1 = 0; end if; end if; end process; process(clkin) begin if(clkinevent and clkin=0) then -下降沿计数 if(cnt2N-1) then cnt2 = cnt2+1; else cnt2 = 0; end if; end if; end process; clkout = 1 when cnt1(N-1)/2 or cnt2(N-1)/2 else 0;end a;例5-11占空比可调的分频

18、器设计，clkin为输入信号，clkout为输出信号，其占空比为m:n，分频比为n，VHDL语言描述的程序如下：Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity fdiv is generic( n: integer:=10; m: integer:=3 -占空比m:n，rate=n ); port( clkin: IN std_logic; clkout: OUT std_logic );End fdiv;architectu

19、re a of fdiv is signal cnt: integer range 0 to n-1;begin process(clkin) begin if(clkinevent and clkin=1) then if(cntn-1) then cnt = cnt+1; else cnt = 0; end if; end if; end process; clkout = 1 when cnt LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S LED7S = “0000000 ; END CASE ; END PROC

20、ESS ;END one;例5-13七段数码管动态显示VHDL程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Seg7_Dsp isPORT(clk: IN std_logic; - CLOCKsegout: OUT std_logic_vector(0 to 6); -段码(dp)selout: OUT std_logic_vector(0 to 5); -6个数码管片选端NumA:IN integer RANGE 0

21、TO 9);END Seg7_Dsp;ARCHITECTURE a OF Seg7_Dsp IS Signal Counter: integer RANGE 0 TO 5;BeginPROCESS (CLK) - 计数器计数 VARIABLE Num: integer RANGE 0 TO 9; BeginIF rising_edge(CLK) THEN IF Counter = 5 then Counter =0; Else Counter selout selout selout selout selout selout selout segout segout segout segout

22、 segout segout segout segout segout segout segout = “0000000 ; END CASE ; END IF ; END PROCESS ;END ;5.5键盘接口电路的VHDL设计例5-14矩阵式键盘扫描程序LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL ;ENTITY keyboard IS PORT (CLK : IN STD_LOGIC ; -扫描时钟频率不宜过高，1KHz以下K

23、IN : IN std_logic_vector(0 to 2); -读入列码Scansignal : OUT std_logic_vector(0 to 3); -输出行码（扫描信号）Num : OUT integer RANGE 0 to 12 -输出键值); END ; ARCHITECTURE scan OF keyboard ISSignal Scans : std_logic_vector(0 to 7); Signal SCN : std_logic_vector(0 to 3); Signal Counter : integer RANGE 0 to 3; -计数产生扫描信号B

24、egin PROCESS (Clk) Begin IF rising_edge(CLK) then IF Counter=3 THEN Counter=0; ELSE Counter SCN SCN SCN SCN Num Num Num Num Num Num Num Num Num Num Num Numnull; END CASE； END IF;END PROCESS; Scans=SCN&KIN; Scansignal=SCN; END;例5-15键盘消抖程序Library ieee;Use ieee.std_logic_1164.all;ENTITY Antiwrite IS PO

25、RT(CLK : IN STD_LOGIC; NumIn: OUT integer RANGE 0 to 12; Numout : OUT integer RANGE 0 to 12 ); END ; ARCHITECTURE Behavior OF Antiwrite ISSignal TempNum : std_logic_vector(0 to 12);Signal Counter : integer RANGE 0 to 31;BEGIN PROCESS (Clk) Begin IF rising_edge(CLK) then TempNum=12； -上电对输出键值赋予无效值Numo

26、ut=12； IF NumIn/= TempNum THEN -上一键值与此键值不同 TempNum= NumIn; -记录该键值 Counter=0; -计数器清零，准备计时 ELSE IF Counter=31 THEN -键值保持31个时钟周期不变时 Numout= NumIn; -确认为有效键值，并且输出 Counter=0; ELSE Counter = Counter+1; END IF; END IF;END IF; END PROCESS ;END Antiwrite;例5-16三态门的描述方法1LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.AL

27、L ;ENTITY tri_gate ISPORT (din, en : IN STD_LOGIC; dout : OUT STD_LOGIC) ; END tri_gate ;ARCHITECTURE zas OF tri_gate ISBEGINTri_gate1: PROCESS (din, en)BEGINIF (en) = 1 THENdout = din ;ELSEdout = Z ; -注意Z要大写END IF ; END PROCESS ;END zas ;例5-17三态门的描述方法2LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ;ENT

28、ITY tri_gate ISPORT (din, en : IN STD_LOGIC; dout : OUT STD_LOGIC) ; END tri_gate ;ARCHITECTURE zas OF tri_gate ISBEGINTri_gate2:BEGINdout = din WHEN en=1 ELSE Z ; -用并行信号赋值END zas ;例5-18单向总线驱动器的描述方法LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ;ENTITY tri_buf8 IS PORT (din : IN Std_Logic_Vector(7 downt

29、o 0); en : IN STD_LOGIC; dout : OUT Std_Logic_Vector(7 downto 0) BUS ) ; END tri_buf8 ; ARCHITECTURE zas OF tri_buf8 ISBEGINTri_buff: PROCESS (din, en)BEGINIF (en) = 1 THENdout = din ;ELSEdout = “ZZZZZZZZ” ; END IF ; END PROCESS ;END zas ;例5-19 双向总线驱动器的描述方法LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL

30、;ENTITY tri_bigate IS PORT (a, b : INOUT Std_Logic_Vector(7 downto 0) BUS; en : IN STD_LOGIC; dir : OUT Std_Logic) ; END tri_bigate ; ARCHITECTURE tri OF tri_bigate ISSigal aout, bout: Std_Logic_Vector(7 downto 0) ;BEGIN PROCESS (a, dir, en)BEGINIF (en = 0) AND (dir = 1) THENbout = a ;ELSEbout = “ZZZZZZZZ” ; END IF ; b = bout ; END PROCESS ; PROCESS (b, dir, en) BEGINIF (en = 0) AND (dir = 0) THENaout = b ;ELSEaout = “ZZZZZZZZ” ; END IF ; a = aout ; END PROCESS ;END tri ; PROCESS (b, dir, en) BEGINIF (en = 0) AND (dir = 0) THENaout = b ;ELSEaout = “ZZZZZZZZ” ; END IF ; a = aout ; END PROCESS