IC工艺集成简介课件.pptx

1、什么是IC FAB的产品？+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道back end(After CT)前道Front end(Before and including CT)Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact

2、module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleProcess flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal

3、1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+N+N+P-Gate(Metal)SourceDrainProcess flowCMOS Front End active area channel doping gate electrode source/drain extensions spa

4、cers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+Isolation（隔离） A.Why do we need Isolati

5、on B.Basic LOCOS process C.Birds beak effect D.Shallow Trench IsolationWhy do we need isolation?So the purpose of isolation is:Electrical isolation between adjacent devicesDefinition of the active area region of the transistorP-WellN-Wellp+P+P+N+N+P ChannelN ChannelParasitic P ChannelParasitic N Cha

6、nnelMethods of Isolation Conventional:Local Oxidation of Silicon(LOCOS) New: Shallow Trench Isolation(STI)BASIC LOCOS PROCESS(1)Pad oxideSi3N4 Pad oxide-Thermal oxidation CVD Si3N4 Mask Photo Etching Strip场氧BASIC LOCOS PROCESS(2) Field oxidation（LOCOS）： 3000 4000A 900C-1000C, 48h, wet O2P-WellN-Well

7、p+场氧 Etching Si3N4/SiO2LOCOSs limitationLOCOS is appropriate for CMOS down to around 1 umLimiting factors:birds beak formationnitride liftingBirds beak dimensions can be reduced by:increasing nitride thicknessdecreasing pad oxide thicknessBUT this increases mechanical stress and can create defects i

8、n siliconNew technique required for sub 0.18um CMOSShallow Trench Isolation (STI)Shallow Trench Isolation(STI) Dry etch a shallow trench CVD SiO2 Etch back SiO2Advantage : no BB effectmeet 0.35um process good planarizationProcess flowCMOS Front End active area channel doping gate electrode source/dr

9、ain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+阱阱 WELLWELL 介绍介绍阱的形成

10、阱的形成单阱双阱技术单阱双阱技术工艺工艺Well (Tube)Well (Tube)为什么要用：可以在衬底上同时制造N/PMOS掺杂类型 Doping type B+-P-well P+-N-well CMOSWellNWellPP-WELL N-WELLsub形成形成在P/N衬底上掺杂B+/P+注入/扩散适当的深度掺杂范围：28*1012/cm2注入能量100250kev +thermal drive-in N-well掩蔽层:氧化硅 400A 光刻N-well：开出N阱N-well 注入: P, 250keV, 0.9E13 atoms/cm2阱推进（退火）Substrate+ + + +

11、 + +P+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +退火：使杂质均匀分布，同时除去（减少）由注入引起的缺陷至此形成均匀的双阱结构光刻P-well：开出P阱P-well 注入: B, 180keV, 8.5E12 atoms/cm2推进B+P-WellN-Well+ + + + + + + + + + + + + + + + + + + + +Single well & Twin well 技术技术Single well n well in p substrate or p well in n substraten-

12、wellP+P+n+p substrate+ + +Transistor in well had lowered mobility due to high level of well counter dopingSimpler processSingle well & Twin well 技术技术Double well(“Twin tub”) -Lightly doped p-substrate Form both n and p welln-wellP+P+n+p substraten+p-wellAllows well profiles to beseparately optimized

13、for each transistor工艺工艺1.Thermal Drive-in 离子注入离子注入+ +长时间高温退火长时间高温退火（drive-indrive-in）P-subP+EpiB+注入能量低注入能量低-表面浓度最高表面浓度最高 ADVANTAGES：不需要高能离子注入机，成本低不需要高能离子注入机，成本低DISADVANTAGES：离子横向扩散导致离子横向扩散导致well尺寸增大尺寸增大 -芯片尺寸增大芯片尺寸增大表面注入浓度大表面注入浓度大沟道中电子沟道中电子/空穴迁移率下降空穴迁移率下降性能下降性能下降2. High Energy Implant (Retrograde we

14、ll) 高能离子注入无需高能离子注入无需drive-inP-subP+EpiB+Retrograde wellPeak well doping below surfaceADVANTAGES:减小横向扩散，减小横向扩散，Well尺寸小尺寸小表面注入浓度小表面注入浓度小沟道中电子沟道中电子/空空穴迁移率大穴迁移率大性能好性能好DISADVANTAGES:需要高能离子注入，成本高需要高能离子注入，成本高Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacer

15、s Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+gate module(1)purposegrowth gate oxidedef

16、ine gate electrodesgate module(2)Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module p

17、assivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+Pp+source/drain extensionspurposelimit hot carrier degradationoptimize drive current/transistor performancehowcontrol maximum electrical field in channel regionoptimization of 2-dimensional doping profile which co

18、mpromises betweenshort channel effects, series resistance, leakage current, drive current .source/drain extensions（2）Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1

19、 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+spacer module(1)purposerealize offset for highly doped junctionsavoid bridging of silicide between gate electrode and junctio

20、nsspacer module(2)Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation modu

21、leCMOS的基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+junction module（1）purposerealize source and drain regions for transistordoping polysilicon gate electrodes : n-type for NMOS, p-type for PMOSjunction module（2）Process flowCMOS Front End active area channel doping gate electr

22、ode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation modulesalicide modulepurposereduce resistance poly lines and source/drain regionsProces

23、s flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + +

24、 + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)后道的基本组成Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module

25、 Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)PMD moduleProcess flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL Salic

26、ideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)Contact moduleProcess flowCMOS Front End

27、 active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + + + + + + + + + + + +

28、 + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)Contact moduleProcess flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 m

29、odule via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)IMD module (1)IMD MODULE (2)Process flowCMOS Front End active area channel doping gate electrode source/drain extensions spacers Junctions LOCSAL

30、SalicideAL BEOL process flow PMD module contact module Al metal 1 module IMD 1 module via 1 module Al metal 2 module via 2 module Al metal 3 module passivation moduleCMOS 基本结构+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)VIA1 MODULE (1) VIA1 MODULE (2)VIA1

31、 MODULE (3)VIA1 MODULE (4)Finally.+ + + + + + + + + + + + + + + + + + + + + N-Well P-Well场氧n+n+p+p+后道（back end)前道（front end)衬底,P型硅片材料检验原始材料: P型Si(100),15-25 .cm.激光标号(Laser Mark)：在晶片边缘刻上批号RCA清洗：RC1：去有机杂质和颗粒RC2：去金属杂质2022-4-2275P+ + + + + + + + + + +N-well掩蔽层:氧化硅 400A 光刻N-well：开出N阱N-well 注入: P, 250keV,

32、 0.9E13 atoms/cm2去胶2022-4-2276+ + + + + + + + + + + + + + + + + + + + +B+光刻P-well：开出P阱P-well 注入: B, 180keV, 8.5E12 atoms/cm2去胶2022-4-2277+ + + + + + + + + + + + + + + + + + + + +阱推进（退火）:X jn-well =2.9 m退火：使杂质均匀分布，同时除去（减少）由注入引起的缺陷至此形成均匀的双阱结构 N-Well P-Well2022-4-2278+ + + + + + + + + + + + + + + + + +

33、 + + + + + + + + + BF2光刻场区：开出场区P-阱区场氧注入：BF2，80keV，4E13场氧注入：提高寄生场管的开启电压，防止寄生三极管的导通 N-Well P-Well去胶2022-4-2279+ + + + + + + + + + + + + + + + + + + + + + + + + + + 基氧 200A 基氧用来缓解Si3N4与硅衬底之间的应力漂光SiO2沉积Si3N4（1500A）Si3N4层被用作为有源区在场氧化时的掩蔽层光刻有源区(Diffusion)：将场区窗口开出刻蚀有源区：氮化硅+氧化硅刻蚀去胶 N-Well P-Well2022-4-2280+

34、+ + + + + + + + + + + + + + + + + + + + + + + + + + 场氧化（LOCOS）：3000 4000A腐蚀Si3N4/SiO2 N-Well P-Well场氧 N-Well P-Well2022-4-2281+ + + + + + + + + + + + + + + + + + + + + + + + + + + NMOS防穿通及阈值电压调整注入：预氧化：200A光刻VTDV Vtn 注入: B11 , 10kev ,1.2E+12/cm2.VTDV注入: NMOS防穿通注入; B11, 50KeV, 1.0E+12 /cm2.Vtn 注入:调制阈值

35、电压防穿通注入：以防止有源区源漏之间相互穿通。 N-Well P-Well场氧去胶2022-4-2282+ + + + + + + + + + + + + + + + + + + + + + + + + + + PMOS防穿通及阈值电压调整注入：光刻VTNH;VTNH 注入:PMOS防穿通注入 As,150kev 2. 0E+11/cm2Vtp 注入 As,35 keV,5.0E+11/cm2去胶 N-Well P-Well场氧2022-4-2283+ + + + + + + + + + + + + + + + + + + + +预栅氧化清洗(pre-gate clean): RCA+稀释的H

36、F酸清洗目的是得到清洁而完整的单晶硅表面，这对确保栅氧层的高质量非常重要。场氧 N-Well P-Well2022-4-2284+ + + + + + + + + + + + + + + + + + + + +场氧栅氧化硅: 70A 3.3V; 110A 5V有干氧和湿氧之分 N-Well P-Well2022-4-2285+ + + + + + + + + + + + + + + + + + + + +多晶淀积(原位掺杂)：3000APre-clean using HF vaporWSix 淀积：1250A减少多晶条上的接触电阻(Polycide)多晶光刻 刻蚀多晶场氧 N-Well P-W

37、ell2022-4-2286+ + + + + + + + + + + + + + + + + + + + + 去胶场氧 N-Well P-Well2022-4-2287+ + + + + + + + + + + + + + + + + + + + +多晶氧化:100A （或者沉积一层薄的TEOS膜）多晶氧化：修复因多晶刻蚀而造成的多晶边缘栅氧的损伤，同时保护多晶条场氧 N-Well P-Well2022-4-2288+ + + + + + + + + + + + + + + + + + + + +AsN管LDD:(减缓热载流子效应(Hot Carrier Effect)NLDD光刻NLDD

38、注入 As, 25kev,3E13 /cm2WSix 退火: RTP, 1000C, 10” N-Well P-Well场氧2022-4-2289+ + + + + + + + + + + + + + + + + + + + +BF2P管LDD光刻PLDDPLDD注入 BF2, 10keV, 1.3E13 /cm2 N-Well P-Well场氧2022-4-2290+ + + + + + + + + + + + + + + + + + + + +边墙形成TEOS 淀积： T=2000ATEOS增密（退火）边墙刻蚀边墙用来隔离源（漏）与栅极 N-Well P-Well场氧2022-4-2291

39、+ + + + + + + + + + + + + + + + + + + + +N管源漏区光刻N+区N+注入 As,3E+15 /cm2 N-Well P-Well场氧n+n+2022-4-2292+ + + + + + + + + + + + + + + + + + + + +P管源漏区光刻P+区区注入BF2 20keV, 2E+15/cm2源漏退火RTP:1020C, 10”源漏结深X JN+ =0.18 m ,X JP+ =0.18 m N-Well P-Well场氧n+n+p+p+2022-4-2293+ + + + + + + + + + + + + + + + + + + + +

40、金属前绝缘介质层（PMD）淀积SiON:LPCVD, 800C,25-35nm淀积TEOS:CVD,720C,100 nm.淀积BPSG APCVD 1000nm B 3.6%;P4.0%BPSG 增密RTP700C 30 min化学机械抛光CMP-PMD N-Well P-Well场氧n+n+p+p+2022-4-2294+ + + + + + + + + + + + + + + + + + + + +淀积氧化硅USG APCVD：400nm接触孔光刻接触孔刻蚀:去胶 N-Well P-Well场氧n+n+p+p+2022-4-2295+ + + + + + + + + + + + + +

41、+ + + + + + +接触孔阻挡层淀积Ti/TiN: 25 nm. TiN可以阻止W与周围介质(Si)之间的反应和元素扩散，同时可增强钨与介质之间的黏着力，但电阻率太高。 Ti用来降低电阻率。W-CVD 淀积: 300 nm.W-返腐蚀(Etch-back) （或者W-CMP） N-Well P-Well场氧n+n+p+p+2022-4-2296+ + + + + + + + + + + + + + + + + + + + +金属夹层淀积： Ti/Al(Cu)/Ti/TiN Al(Cu) : 5500A.TiN：电阻率较高。顶层TiN作为光刻的ARC(抗反射层）。 Ti和TiN还可阻止金属

42、与介质之间的元素扩散。Al(CuSi)：铝中掺少量铜或硅可以增强铝线的抗电迁移性能。Ti/TiNTiAl(Cu) N-Well P-Well场氧n+n+p+p+2022-4-2297+ + + + + + + + + + + + + + + + + + + + +金属1光刻金属1刻蚀去胶 N-Well P-Well场氧n+n+p+p+2022-4-2298+ + + + + + + + + + + + + + + + + + + + +金属1-2间介质淀积及平坦化氧化层淀积 1500 nm, HDP , 400C; 750nm ,PECVD,400C.化学机械抛光 N-Well P-Well场

43、氧n+n+p+p+2022-4-2299+ + + + + + + + + + + + + + + + + + + + +通孔1光刻通孔1刻蚀通孔阻挡层淀积 Ti/TiN: 25 nm.W-CVD 淀积: 600 nm.W-返腐蚀(Etch-back) N-Well P-Well场氧n+n+p+p+2022-4-22100+ + + + + + + + + + + + + + + + + + + + +金属2淀积 Al(Cu): 5400A.金属2光刻金属2刻蚀去胶 N-Well P-Well场氧n+n+p+p+2022-4-22101+ + + + + + + + + + + + + + + + + + + + +钝化层淀积 PECVD SiO2+SiN钝化层光刻钝化层刻蚀合金化 H2/N2,400C,20分去胶 N-Well P-Well场氧n+n+p+p+